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mixed signal isp flash mcu family c8051f336/7/8/9 rev. 0.2 8/07 copyright ? 2007 by si licon laboratories c8051f336/7/8/9 this information applies to a product under dev elopment. its characteristics and specifications are s ubject to change without n otice. analog peripherals - 10-bit adc (?f336/8 only) ? up to 200 ksps ? up to 20 external single-ended or differential inputs ? vref from on-chip vref, external pin or v dd ? internal or external start of conversion source ? built-in temperature sensor - 10-bit current output dac (?f336/8 only) - comparator ? programmable hysteresis and response time ? configurable as interrupt or reset source on-chip debug - on-chip debug circuitry facilitates full speed, non- intrusive in-system debug (no emulator required) - provides breakpoints, single stepping, inspect/modify memory and registers - superior performance to emulation systems using ice-chips, target pods, and sockets - low cost, complete development kit supply voltage 2.7 to 3.6 v - built-in voltage supply monitor high-speed 8051 c core - pipelined instruction architecture; executes 70% of instructions in 1 or 2 system clocks - up to 25 mips throughput with 25 mhz clock - expanded interrupt handler temperature range: ?40 to +85 c memory - 768 bytes internal data ram (256 + 512) - 16 kb flash; in-system programmable in 512-byte sectors (512 bytes are reserved) digital peripherals - 21 or 17 port i/o; all 5 v tolerant with high sink current - pin-compatible with c8051f330 family of mcus - hardware enhanced uart, smbus? (i 2 c compati - ble), and enhanced spi? serial ports - four general purpose 16-bit counter/timers - 16-bit programmable counter array (pca) with three capture/compare modules and enhanced pwm functionality - real time clock mode using timer and crystal clock sources - 24.5 mhz 2% oscillator ? supports crystal-less uart operation ? low-power suspend mode with fast wake time - 80/20/40/10 khz low-frequency, low-power oscillator - external oscillator: crystal, rc, c, or clock (1 or 2 pin modes) - can switch between clock s ources on-the-fly; useful in power saving modes 20 or 24-pin qfn (4 x 4 mm) analog peripherals 16 kb isp flash 768 b sram por debug circuitry flexible interrupts 8051 cpu (25 mips) digital i/o 24.5 mhz precision internal oscillator high-speed controller core crossbar voltage comparator + ? wdt uart smbus pca timer 0 timer 1 timer 2 timer 3 port 0 spi low frequency internal oscillator port 1 p2.0? p2.3* ?f336/8 only p2.4* 10-bit 200 ksps adc temp sensor a m u x 10-bit current dac *p2.1?2.4 qfn24 only
c8051f336/7/8/9 2 rev. 0.2
rev. 0.2 3 c8051f336/7/8/9 table of contents 1. system overview............ ................ ................ ................. .............. .............. ........... 16 1.1. cip-51? microcontroller core.. ................ ................. .............. .............. ........... 19 1.1.1. fully 8051 compatible...... ................ ................. .............. .............. ........... 19 1.1.2. improved throughput ............ .............. .............. .............. .............. ........... 19 1.1.3. additional features .......... ................ ................. .............. .............. ........... 19 1.2. on-chip memory......... ................ ................. .............. .............. .............. ........... 20 1.3. on-chip debug circuitr y.................... ................. ................ ................. ............. 21 1.4. programmable digital i/o and crossbar ............... ................. ................ ........... 22 1.5. serial ports ............ ................. ................ ................ ................. .............. ........... 23 1.6. programmable counter array ... ................ ................. .............. .............. ........... 23 1.7. 10-bit analog to digital conver ter.................... .............. ............... ........... ......... 24 1.8. comparator ............... ................ ................ ................. .............. .............. ........... 25 1.9. 10-bit current output dac...... ................ ................ ................. .............. ........... 26 2. ordering information...... ................ ................ ................. .............. .............. ........... 27 3. pin definitions ............. ................. ................ ................ ................. .............. ........... 28 4. qfn-20 package specifications.... ................ ................. .............. .............. ........... 32 5. qfn-24 package specifications.... ................ ................. .............. .............. ........... 33 6. electrical characteristics.......... ................. ................ ................. ................ ........... 34 6.1. absolute maximum specificati ons ...................... ................ ................. ............. 34 6.2. electrical characterist ics.................. .............. .............. .............. .............. ......... 35 7. 10-bit adc (adc 0, c8051f336/8 only) ......... ................. .............. .............. ........... 43 7.1. output code formatting ......... ................ ................ ................. .............. ........... 44 7.2. modes of operation ............. ................. ................ ................. ................ ........... 44 7.2.1. starting a conversion....... ................ ................. .............. .............. ........... 44 7.2.2. tracking modes................ ................ ................. .............. .............. ........... 45 7.2.3. settling time r equirements ................ .............. .............. .............. ........... 47 7.3. programmable window detector ................. .............. .............. .............. ........... 51 7.3.1. window detector in sing le-ended mode .......... .............. .............. ........... 53 7.3.2. window detector in differential mode..... .............. ............... ........... ......... 54 7.4. adc0 analog multiplexer (c 8051f336/8 only) .......... .............. .............. ........... 55 8. temperature sensor (c8051f336/8 only) ................. ................. ................ ........... 58 9. 10-bit current mode dac (ida 0, c8051f336/8 only)............. ................. ............. 59 9.1. ida0 output scheduling . ................. .............. .............. .............. .............. ......... 59 9.1.1. update output on-demand .. .............. .............. .............. .............. ........... 59 9.1.2. update output based on timer overflow ............. ............... ........... ......... 60 9.1.3. update output based on cnvstr edge................... ................. ............. 60 9.2. idac output mapping.......... ................. ................ ................. ................ ........... 60 10. voltage reference (c8051f336/8 only).............. .............. .............. .............. ......... 63 11. comparator0 ................ ................. ................ ................ ................. .............. ........... 65 11.1.comparator multiplexer ....... ................. ................ ................. ................ ........... 70 12. cip-51 microcontroller .............. ................. ................ ................. ................ ........... 72 12.1.instruction set........... ................ ................ ................. .............. .............. ........... 73 12.1.1.instruction and cpu timing .. .............. .............. .............. .............. ........... 73
c8051f336/7/8/9 4 rev. 0.2 12.2.cip-51 register descriptions ... ................ ................. .............. .............. ........... 78 13. memory organization..... ................ ................ ................. .............. .............. ........... 81 13.1.program memory........ ................ ................. .............. .............. .............. ........... 82 13.1.1.movx instruction and pr ogram memory .......... .............. .............. ........... 82 13.2.data memory ............ ................ ................ ................. .............. .............. ........... 83 13.2.1.internal ram ........ ................. .............. .............. .............. .............. ........... 83 13.2.1.1.general purpose regist ers ............... ................ ................. ............. 83 13.2.1.2.bit addressabl e locations .............. .............. ............... ........... ......... 83 13.2.1.3.stack ............. ................ ................. ................ ................. ............. 84 13.2.2.external ram ....... ................. .............. .............. .............. .............. ........... 84 14. special function registers ...... ................. ................ ................. ................ ........... 85 15. interrupts............. ................ ................. .............. .............. .............. .............. ........... 8 9 15.1.mcu interrupt source s and vectors.............. .............. .............. .............. ......... 90 15.1.1.interrupt priorities........ ................. ................ ................. ................ ........... 90 15.1.2.interrupt latency .............. ................ ................. .............. .............. ........... 90 15.2.interrupt register de scriptions ............. ................ ................. ................ ........... 91 15.3.external interrupts /i nt0 and /int1............. .............. .............. .............. ........... 96 16. flash memory ................. ................ ................ ................. .............. .............. ........... 98 16.1.programming the flash memory ................ .............. .............. .............. ........... 98 16.1.1.flash lock and key functi ons ................ .............. ............... ........... ......... 98 16.1.2.flash erase procedure ...... ................. .............. .............. .............. ........... 98 16.1.3.flash write procedure ..... ................ ................. .............. .............. ........... 99 16.2.non-volatile data storage ... ................. ................ ................. ................ ........... 99 16.3.security options ....... ................ ................ ................. .............. .............. ......... 100 16.4.flash write and erase guidelines ............... .............. .............. .............. ......... 102 16.4.1.v dd maintenance and the v dd monitor ............ .............. .............. ......... 102 16.4.2.pswe maintenance ......... ................ ................. .............. .............. ......... 102 16.4.3.system clock ....... ................. .............. .............. .............. .............. ......... 103 17. power management modes ......... ................ ................ ................. .............. ......... 107 17.1.idle mode............... ................. ................ ................ ................. .............. ......... 107 17.2.stop mode ......... ................ ................ ................. ................ ................. ........... 108 17.3.suspend mode ............. ................. .............. .............. .............. .............. ......... 108 18. reset sources.......... ................ ................ ................. ................ ................. ........... 110 18.1.power-on reset ....... ................ ................ ................. .............. .............. ......... 111 18.2.power-fail reset / vd d monitor ................. .............. .............. .............. ......... 112 18.3.external reset .......... ................ ................ ................. .............. .............. ......... 113 18.4.missing clock detector reset ... ............... ................. .............. .............. ......... 113 18.5.comparator0 reset ............. ................. ................ ................. ................ ......... 114 18.6.pca watchdog timer reset ..... ............... ................. .............. .............. ......... 114 18.7.flash error reset ..... ................ ................ ................. .............. .............. ......... 114 18.8.software reset ......... ................ ................ ................. .............. .............. ......... 114 19. oscillators and clock selection. ................... ................. .............. .............. ......... 116 19.1.system clock selectio n................. .............. .............. .............. .............. ......... 117 19.2.programmable internal hi gh-frequency (h-f) oscillator ... ................. ........... 118 19.2.1.internal oscillator susp end mode ................ ................. ................ ......... 118
rev. 0.2 5 c8051f336/7/8/9 19.3.programmable internal low -frequency (l-f) oscillator .... ................. ........... 120 19.3.1.calibrating the internal l- f oscillator........... ................. ................ ......... 120 19.4.external oscillator drive circuit................ ................. .............. .............. ......... 121 19.4.1.external crystal example. ................ ................. .............. .............. ......... 123 19.4.2.external rc example....... ................ ................. .............. .............. ......... 125 19.4.3.external capacitor exampl e................ .............. .............. .............. ......... 125 20. port input/output............ ................ ................ ................. .............. .............. ......... 126 20.1.port i/o modes of operation ................. ................ ................. ................ ......... 127 20.1.1.port pins configured for analog i/o............. ................. ................ ......... 127 20.1.2.port pins configured for digital i/o...... .............. .............. .............. ....... 128 20.1.3.interfacing port i/o to 5v logic ........... .............. .............. .............. ......... 128 20.2.assigning port i/o pins to analog and digital functions.. ............ ........... ....... 129 20.2.1.assigning port i/o pins to analog functions ...... .............. .............. ....... 129 20.2.2.assigning port i/o pins to digital func tions............. ............ ........... ....... 130 20.2.3.assigning port i/o pi ns to external digital ev ent capture functions .... 130 20.3.priority crossbar decoder ... ................. ................ ................. ................ ......... 131 20.4.port i/o initialization ........ .............. .............. .............. .............. .............. ......... 133 20.5.port match ............. ................. ................ ................ ................. .............. ......... 136 20.6.special function register s for accessing and c onfiguring port i/ o .............. 138 21. smbus ................. ................ ................. .............. .............. .............. .............. ......... 145 21.1.supporting documents ............. ................ ................. .............. .............. ......... 145 21.2.smbus configuration... ............... ................. .............. .............. .............. ......... 146 21.3.smbus operation ....... ................ ................. .............. .............. .............. ......... 146 21.3.1.transmitter vs. receiver.. ................ ................. .............. .............. ......... 147 21.3.2.arbitration......... ................ ................ ................. .............. .............. ......... 147 21.3.3.clock low extension........ ................ ................. .............. .............. ......... 148 21.3.4.scl low timeout.... .............. .............. .............. .............. .............. ......... 148 21.3.5.scl high (smbus free) ti meout .............. ................ ................. ........... 148 21.4.using the smbus........ ................ ................. .............. .............. .............. ......... 148 21.4.1.smbus configuration regist er................ .............. ............... ........... ....... 149 21.4.2.smb0cn control register . ................. .............. .............. .............. ......... 152 21.4.2.1.software ack generati on ............ .............. .............. .............. ....... 152 21.4.2.2.hardware ack generatio n .................... ................. .............. ......... 152 21.4.3.hardware slave address recognition ........... ................. .............. ......... 155 21.4.4.data register ....... ................. .............. .............. .............. .............. ......... 157 21.5.smbus transfer modes... .............. .............. .............. .............. .............. ......... 158 21.5.1.write sequence (master) ...... .............. .............. .............. .............. ......... 158 21.5.2.read sequence (master) ...... .............. .............. .............. .............. ......... 159 21.5.3.write sequence (slave) ........ .............. .............. .............. .............. ......... 160 21.5.4.read sequence (slave) ........ .............. .............. .............. .............. ......... 161 21.6.smbus status decoding ................ .............. .............. .............. .............. ......... 161 22. uart0................ ................ ................ ................. .............. .............. .............. ......... 166 22.1.enhanced baud rate g eneration.................. .............. .............. .............. ....... 167 22.2.operational modes ....... ................. .............. .............. .............. .............. ......... 168
c8051f336/7/8/9 6 rev. 0.2 22.2.1.8-bit uart ........... ................. .............. .............. .............. .............. ......... 168 22.2.2.9-bit uart ........... ................. .............. .............. .............. .............. ......... 169 22.3.multiprocessor communications ... .............. .............. .............. .............. ......... 169 23. enhanced serial peripheral interface (spi0)..... .............. .............. .............. ....... 174 23.1.signal descriptions....... ................. .............. .............. .............. .............. ......... 175 23.1.1.master out, slave in (mos i)...................... ................ ................. ........... 175 23.1.2.master in, slave out (miso)............... .............. .............. .............. ......... 175 23.1.3.serial clock (sck) ........... ................ ................. .............. .............. ......... 175 23.1.4.slave select (nss) .......... ................ ................. .............. .............. ......... 175 23.2.spi0 master mode operation . ................ ................ ................. .............. ......... 176 23.3.spi0 slave mode operation ..... ................ ................. .............. .............. ......... 178 23.4.spi0 interrupt sources ........ ................. ................ ................. ................ ......... 178 23.5.serial clock phase and polari ty ............. ................ ................. .............. ......... 179 23.6.spi special function registers . ............... ................. .............. .............. ......... 180 24. timers................ ................ ................ .............. .............. ............... .............. ........... 18 7 24.1.timer 0 and ti mer 1 ............... ................ ................ ................. .............. ......... 189 24.1.1.mode 0: 13-bit counter/timer ................. .............. ............... ........... ....... 189 24.1.2.mode 1: 16-bit counter/timer ................. .............. ............... ........... ....... 190 24.1.3.mode 2: 8-bit counter/tim er with auto-reload.......... ................. ........... 191 24.1.4.mode 3: two 8-bit counter /timers (timer 0 only)..... ................. ........... 192 24.2.timer 2 ............. ................ ................ ................. ................ ................. ........... 197 24.2.1.16-bit timer with auto-rel oad............... .............. .............. .............. ....... 197 24.2.2.8-bit timers with auto-rel oad............... .............. .............. .............. ....... 198 24.2.3.low-frequency oscillator (lfo) capture mode ........ ................. ........... 199 24.3.timer 3 ............. ................ ................ ................. ................ ................. ........... 203 24.3.1.16-bit timer with auto-rel oad............... .............. .............. .............. ....... 203 24.3.2.8-bit timers with auto-rel oad............... .............. .............. .............. ....... 204 24.3.3.low-frequency oscillator (lfo) capture mode ........ ................. ........... 205 25. programmable counter array ....... ................ ................. .............. .............. ......... 209 25.1.pca counter/timer ............. ................. ................ ................. ................ ......... 210 25.2.pca0 interrupt sources....... ................. ................ ................. ................ ......... 211 25.3.capture/compare modules ...... ................ ................. .............. .............. ......... 212 25.3.1.edge-triggered captur e mode................. .............. ............... ........... ....... 213 25.3.2.software timer (compare) mode................. ................. ................ ......... 214 25.3.3.high-speed output mode ..... .............. .............. .............. .............. ......... 215 25.3.4.frequency output mode ....... .............. .............. .............. .............. ......... 216 25.3.5. 8-bit, 9-bit, 10-bit and 11-bit pulse width modulat or modes ....... ......... 217 25.3.5.1. 8-bit pulse width modulator mode....... ................. .............. ......... 217 25.3.5.2. 9/10/11-bit pulse width modulator mode......... ................. ........... 219 25.3.6. 16-bit pulse width m odulator mode........... ................. ................ ......... 220 25.4.watchdog timer mode .... .............. .............. .............. .............. .............. ......... 221 25.4.1.watchdog timer operation ... .............. .............. .............. .............. ......... 221 25.4.2.watchdog timer usage ........ .............. .............. .............. .............. ......... 222 25.5.register descriptions for pca0 ................ ................. .............. .............. ......... 223
rev. 0.2 7 c8051f336/7/8/9 26. c2 interface ................ ................ ................. ................ ................. ................ ......... 229 26.1.c2 interface registers......... ................. ................ ................. ................ ......... 229 26.2.c2 pin sharing ......... ................ ................ ................. .............. .............. ......... 232 contact information.......... ................. ................ ................ ................. .............. ........ 234
c8051f336/7/8/9 8 rev. 0.2 list of figures 1. system overview figure 1.1. c8051f336/7 block di agram .............. .............. .............. .............. ......... 17 figure 1.2. c8051f338/9 block di agram .............. .............. .............. .............. ......... 18 figure 1.3. on-chip clock and rese t ................. .............. .............. .............. ........... 20 figure 1.4. on-chip memory map. ................... ................. .............. .............. ........... 21 figure 1.5. digital cro ssbar diagram ............... ................. .............. .............. ........... 22 figure 1.6. pca block diagram ..... ................ ................ ................. .............. ........... 23 figure 1.7. pca block diagram ..... ................ ................ ................. .............. ........... 23 figure 1.8. 10-bit adc block diagr am................ .............. .............. .............. ........... 24 figure 1.9. comparator0 block di agram.................... ................ ................. ............. 25 figure 1.10. ida0 functional bl ock diagram ............. ................ ................. ............. 26 2. ordering information 3. pin definitions figure 3.1. qfn-20 pinout diagr am (top view) .......... ................. ................ ........... 30 figure 3.2. qfn-24 pinout diagr am (top view) .......... ................. ................ ........... 31 4. qfn-20 package specifications figure 4.1. qfn-20 package drawin g ................ .............. .............. .............. ........... 32 5. qfn-24 package specifications figure 5.1. qfn-24 package drawin g ................ .............. .............. .............. ........... 33 6. electrical characteristics 7. 10-bit adc (adc0, c8051f336/8 only) figure 7.1. adc0 functional bl ock diagram.............. ................ ................. ............. 43 figure 7.2. 10-bit adc track and conversion example timing ................. ............. 46 figure 7.3. adc0 equiva lent input circuits. ............... ................ ................. ............. 47 figure 7.4. adc window compare example: right-jus tified single-ended data ... 53 figure 7.5. adc window co mpare example: left-justifi ed single-ended data ..... 53 figure 7.6. adc window co mpare example: right-justifi ed differential data ....... 54 figure 7.7. adc window com pare example: left-justified di fferential data.......... 54 figure 7.8. adc0 multiplexer bl ock diagram............. ................ ................. ............. 55 8. temperature sens or (c8051f336/8 only) figure 8.1. temperature sensor transfer function ..... ................. ................ ........... 58 9. 10-bit current mode dac (ida0, c8051f336/8 only) figure 9.1. ida0 functional blo ck diagram ............... ................ ................. ............. 59 figure 9.2. ida0 data word m apping .............. ................. .............. .............. ........... 60 10. voltage reference (c8051f336/8 only) figure 10.1. voltage reference functional block diagram...... ............ ........... ......... 63 11. comparator0 figure 11.1. compar ator0 functional block diagram ....... .............. .............. ........... 65 figure 11.2. compar ator hysteresis pl ot ................ .............. ............... ........... ......... 66 figure 11.3. compar ator input multiplexer block diagram .............. .............. ........... 70 12. cip-51 microcontroller figure 12.1. cip-51 block diagram.............. ................ ................. ................ ........... 72
rev. 0.2 9 c8051f336/7/8/9 13. memory organization figure 13.1. c8051f336/7/8 /9 memory map......... .............. .............. .............. ......... 81 figure 13.2. flash program memo ry map.................. ................ ................. ............. 82 14. special function registers 15. interrupts 16. flash memory figure 16.1. flash program memo ry map.................. ................ ................. ........... 100 17. power management modes 18. reset sources figure 18.1. rese t sources.............. ................ ................. .............. .............. ......... 110 figure 18.2. power-on and vdd monitor reset timing ....... ............... ........... ....... 111 19. oscillators and clock selection figure 19.1. oscillator options ................ .............. .............. .............. .............. ....... 116 figure 19.2. external 32.768 khz quartz crystal oscillat or connection diagram . 124 20. port input/output figure 20.1. port i/o functional block diagram ................ .............. .............. ......... 127 figure 20.2. port i/o ce ll block diagram ............ .............. .............. .............. ......... 128 figure 20.3. crossbar priority decoder with no pins sk ipped ............... ................ 131 figure 20.4. crossbar priority decoder with crystal pins skipped .......... .............. 132 21. smbus figure 21.1. smbus block diagram ............. ................ ................. ................ ......... 145 figure 21.2. typical smbu s configuration .......... .............. .............. .............. ......... 146 figure 21.3. smbus transac tion ............. .............. .............. .............. .............. ....... 147 figure 21.4. typical sm bus scl generation........ .............. .............. .............. ....... 150 figure 21.5. typical ma ster write sequence ........ .............. .............. .............. ....... 158 figure 21.6. typical ma ster read sequence ........ .............. .............. .............. ....... 159 figure 21.7. typical slave writ e sequence ................. ................. ................ ......... 160 figure 21.8. typical sl ave read sequence .......... .............. .............. .............. ....... 161 22. uart0 figure 22.1. uart0 block diagram ............. ................ ................. ................ ......... 166 figure 22.2. uart0 baud rate logic ............ ................ ................. .............. ......... 167 figure 22.3. uart interconnect di agram ............. .............. .............. .............. ....... 168 figure 22.4. 8-bit uart timing diagram............ .............. .............. .............. ......... 168 figure 22.5. 9-bit uart timing diagram............ .............. .............. .............. ......... 169 figure 22.6. uart multi-proc essor mode interconne ct diagram .......... ................ 170 23. enhanced serial peripheral interface (spi0) figure 23.1. spi bl ock diagram ............ .............. .............. .............. .............. ......... 174 figure 23.2. multiple -master mode connection diagram ...... ............... ........... ....... 177 figure 23.3. 3-wi re single master a nd 3-wire single slav e mode connection diagram 177 figure 23.4. 4-wire single master mode and 4-wire slave m ode connection diagram 177 figure 23.5. master mode data/ clock timing .............. ................. ................ ......... 179 figure 23.6. slave mode data/clock timing (ckpha = 0) ... ............... ........... ....... 180 figure 23.7. slave mode data/clock timing (ckpha = 1) ... ............... ........... ....... 180
c8051f336/7/8/9 10 rev. 0.2 figure 23.8. spi ma ster timing (ckpha = 0).. ................. .............. .............. ......... 184 figure 23.9. spi ma ster timing (ckpha = 1).. ................. .............. .............. ......... 184 figure 23.10. spi slave timing (c kpha = 0).............. ................. ................ ......... 185 figure 23.11. spi slave timing (c kpha = 1).............. ................. ................ ......... 185 24. timers figure 24.1. t0 mode 0 bl ock diagram............... .............. .............. .............. ......... 190 figure 24.2. t0 mode 2 bl ock diagram............... .............. .............. .............. ......... 191 figure 24.3. t0 mode 3 bl ock diagram............... .............. .............. .............. ......... 192 figure 24.4. timer 2 16- bit mode block diagram .. ............. .............. .............. ....... 197 figure 24.5. timer 2 8- bit mode block diagram .. ................. ............... ........... ....... 198 figure 24.6. timer 2 low-frequency oscill ation capture mode bl ock diagram.... 199 figure 24.7. timer 3 16- bit mode block diagram .. ............. .............. .............. ....... 203 figure 24.8. timer 3 8- bit mode block diagram .. ................. ............... ........... ....... 204 figure 24.9. timer 3 low-frequency oscill ation capture mode bl ock diagram.... 205 25. programmable counter array figure 25.1. pca block diagram.... ................ ................ ................. .............. ......... 209 figure 25.2. pca counter /timer block diagram.... ............. .............. .............. ....... 210 figure 25.3. pca interrupt blo ck diagram ................. ................ ................. ........... 211 figure 25.4. pca captur e mode diagram............. .............. .............. .............. ....... 213 figure 25.5. pca software time r mode diagram ........ ................. ................ ......... 214 figure 25.6. pca high- speed output mode diagram........... ............... ........... ....... 215 figure 25.7. pca fr equency output mode ......... .............. .............. .............. ......... 216 figure 25.8. pca 8-bit pwm mode diagram .......... .............. ............... ........... ....... 218 figure 25.9. pca 16-bit pwm mode ................ ................. .............. .............. ......... 220 figure 25.10. pca module 2 with watchdog ti mer enabled ..... ................. ........... 221 26. c2 interface figure 26.1. typical c2 pin sharing.......... ................. ................ ................. ........... 232
rev. 0.2 11 c8051f336/7/8/9 list of tables 1. system overview 2. ordering information table 2.1. product selection guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3. pin definitions table 3.1. pin definitions for th e c8051f336/7/8/9 . . . . . . . . . . . . . . . . . . . . . . . . . 28 4. qfn-20 package specifications table 4.1. qfn-20 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5. qfn-24 package specifications table 5.1. qfn-24 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6. electrical characteristics table 6.1. absolute maximum rati ngs ................... .............. ............... ........... ......... 34 table 6.2. global elec trical characteristics .... ............... ................. .............. ........... 35 table 6.3. port i/o dc electrical characteristi cs .............. .............. .............. ........... 36 table 6.4. reset electrical char acteristics ............. .............. ............... ........... ......... 37 table 6.5. flash electrical char acteristics .............. .............. ............... ........... ......... 37 table 6.6. internal hi gh-frequency oscillator electrical characteristics . ................ 38 table 6.7. internal low -frequency oscillator electrical characteristics .. ................ 38 table 6.8. adc0 electrical char acteristics ............. .............. ............... ........... ......... 39 table 6.9. temperature sensor electrical characteristics ... ............... ........... ......... 40 table 6.10. voltage reference el ectrical characteristics ..... ............... ........... ......... 40 table 6.11. idac electric al characteristics ..... ................. .............. .............. ........... 41 table 6.12. comparator el ectrical characteristics ........... .............. .............. ........... 42 7. 10-bit adc (adc0 , c8051f336/8 only) 8. temperature sens or (c8051f336/8 only) 9. 10-bit current mode da c (ida0, c8051f336/8 only) 10. voltage reference (c8051f336/8 only) 11. comparator0 12. cip-51 microcontroller table 12.1. cip-51 instruct ion set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 13. memory organization 14. special function registers table 14.1. special function regi ster (sfr) memory map . . . . . . . . . . . . . . . . . . 85 table 14.2. special function registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 15. interrupts table 15.1. interrupt summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 16. flash memory table 16.1. flash security summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 17. power management modes 18. reset sources 19. oscillators and clock selection 20. port input/output table 20.1. port i/o a ssignment for analog functions . . . . . . . . . . . . . . . . . . . . . 129
c8051f336/7/8/9 12 rev. 0.2 table 20.2. port i/o assi gnment for digital functions . . . . . . . . . . . . . . . . . . . . . 130 table 20.3. port i/o assignmen t for external digital event capture functions . . 130 21. smbus table 21.1. smbus clock source selection .............. ................ ................. ........... 149 table 21.2. minimum sda setup and hold times . . . . . . . . . . . . . . . . . . . . . . . . 150 table 21.3. sources for hardware changes to smb0cn . . . . . . . . . . . . . . . . . . . 154 table 21.4. hardware address recognition ex amples (ehack = 1) . . . . . . . . . . 155 table 21.5. smbus status decoding wi th hardware ack generation disabled (ehack = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 table 21.6. smbus status decoding wi th hardware ack generation enabled (ehack = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 22. uart0 table 22.1. timer settings for standard baud rates using the internal 24.5 mhz o scillator . . . . . . . . . . . . . . . . . . . . . . . 173 table 22.2. timer settings for standard baud rates using an external 22.1184 mhz oscillator . . . . . . . . . . . . . . . . . . . . . 173 23. enhanced serial peripheral interface (spi0) table 23.1. spi slave timing paramete rs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 24. timers 25. programmable counter array table 25.1. pca timebase input opti ons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 table 25.2. pca0cpm and pca0 pwm bit settings for pca capture/compare modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 table 25.3. watchdog timer timeout in tervals1 . . . . . . . . . . . . . . . . . . . . . . . . . 222 26. c2 interface
rev. 0.2 13 c8051f336/7/8/9 list of registers sfr definition 7.1. adc0cf: adc0 c onfiguration . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 sfr definition 7.2. adc0h: adc0 data word msb . . . . . . . . . . . . . . . . . . . . . . . . . . 49 sfr definition 7.3. adc0l: adc0 data word lsb . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 sfr definition 7.4. adc0cn: adc0 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 sfr definition 7.5. adc0gth: a dc0 greater-than data high byte . . . . . . . . . . . . . 51 sfr definition 7.6. adc0gtl: ad c0 greater-than data low byte . . . . . . . . . . . . . . 51 sfr definition 7.7. adc0lth: ad c0 less-than data high byte . . . . . . . . . . . . . . . . 52 sfr definition 7.8. adc0ltl: adc0 less-than data low byte . . . . . . . . . . . . . . . . . 52 sfr definition 7.9. amx0p: amux0 positive channel select . . . . . . . . . . . . . . . . . . . 56 sfr definition 7.10. amx0n: amux 0 negative channel select . . . . . . . . . . . . . . . . . 57 sfr definition 9.1. ida0cn: ida0 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 sfr definition 9.2. ida0h: ida0 da ta word msb . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 sfr definition 9.3. ida0l: ida0 data word lsb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 sfr definition 10.1. ref0cn : reference control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 sfr definition 11.1. cpt0cn : comparator0 control . . . . . . . . . . . . . . . . . . . . . . . . . . 68 sfr definition 11.2. cpt0md: com parator0 mode selection . . . . . . . . . . . . . . . . . . . 69 sfr definition 11.3. cpt0mx: com parator0 mux selection . . . . . . . . . . . . . . . . . . . 71 sfr definition 12.1. dpl: data pointe r low byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 sfr definition 12.2. dph: da ta pointer high byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 sfr definition 12.3. sp: stack pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 sfr definition 12.4. acc: ac cumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 sfr definition 12.5. b: b register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 sfr definition 12.6. psw: program st atus word . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 sfr definition 13.1. emi0cn: external memory interface contro l . . . . . . . . . . . . . . . 84 sfr definition 15.1. ie: interr upt enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 sfr definition 15.2. ip: interr upt priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 sfr definition 15.3. eie1: extended interrupt enable 1 . . . . . . . . . . . . . . . . . . . . . . . 94 sfr definition 15.4. eip1: extended inte rrupt priority 1 . . . . . . . . . . . . . . . . . . . . . . . 95 sfr definition 15.5. it01cf: int0/int 1 configuration . . . . . . . . . . . . . . . . . . . . . . . . 97 sfr definition 16.1. psctl: program store r/w control . . . . . . . . . . . . . . . . . . . . . 104 sfr definition 16.2. flkey: flash lock and key . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 sfr definition 16.3. flscl: flash scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 sfr definition 17.1. pc on: power control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 sfr definition 18.1. vdm0cn : vdd monitor control . . . . . . . . . . . . . . . . . . . . . . . . 113 sfr definition 18.2. rstsrc: reset source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 sfr definition 19.1. clksel: clock select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 sfr definition 19.2. oscicl: intern al h-f oscillator calibration . . . . . . . . . . . . . . . 118 sfr definition 19.3. oscicn: inter nal h-f oscillator control . . . . . . . . . . . . . . . . . . 119 sfr definition 19.4. osclcn: inter nal l-f oscillator control . . . . . . . . . . . . . . . . . . 120 sfr definition 19.5. oscxcn: external oscillator c ontrol . . . . . . . . . . . . . . . . . . . . 122 sfr definition 20.1. xbr0: port i/o crossbar regist er 0 . . . . . . . . . . . . . . . . . . . . . 134 sfr definition 20.2. xbr1: port i/o crossbar regist er 1 . . . . . . . . . . . . . . . . . . . . . 135 sfr definition 20.3. p0mask : port 0 mask register . . . . . . . . . . . . . . . . . . . . . . . . . 136
c8051f336/7/8/9 14 rev. 0.2 sfr definition 20.4. p0mat: port 0 match register . . . . . . . . . . . . . . . . . . . . . . . . . 136 sfr definition 20.5. p1mask : port 1 mask register . . . . . . . . . . . . . . . . . . . . . . . . . 137 sfr definition 20.6. p1mat: port 1 match register . . . . . . . . . . . . . . . . . . . . . . . . . 137 sfr definition 20.7. p0: port 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 sfr definition 20.8. p0mdin : port 0 input mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 sfr definition 20.9. p0mdout: port 0 output mode . . . . . . . . . . . . . . . . . . . . . . . . 139 sfr definition 20.10. p0 skip: port 0 skip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 sfr definition 20.11. p1: port 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 sfr definition 20.12. p1mdin : port 1 input mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 sfr definition 20.13. p1mdout: port 1 output mode . . . . . . . . . . . . . . . . . . . . . . . 141 sfr definition 20.14. p1 skip: port 1 skip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 sfr definition 20.15. p2: port 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 sfr definition 20.16. p2mdin : port 2 input mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 sfr definition 20.17. p2mdout: port 2 output mode . . . . . . . . . . . . . . . . . . . . . . . 143 sfr definition 20.18. p2 skip: port 2 skip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 sfr definition 21.1. smb0cf: smbu s clock/configuration . . . . . . . . . . . . . . . . . . . 151 sfr definition 21.2. smb0cn : smbus control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 sfr definition 21.3. smb0a dr: smbus slave address . . . . . . . . . . . . . . . . . . . . . . 156 sfr definition 21.4. smb0adm: sm bus slave address mask . . . . . . . . . . . . . . . . . 156 sfr definition 21.5. smb0dat: smbus data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 sfr definition 22.1. scon0: serial port 0 control . . . . . . . . . . . . . . . . . . . . . . . . . . 171 sfr definition 22.2. sbuf0: serial (uart0) port data buffer . . . . . . . . . . . . . . . . . 172 sfr definition 23.1. spi0cf g: spi0 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 181 sfr definition 23.2. spi0cn: spi0 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 sfr definition 23.3. spi0ck r: spi0 clock rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 sfr definition 23.4. spi0dat: spi0 data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 sfr definition 24.1. ckcon: clock control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 sfr definition 24.2. tcon: timer cont rol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 sfr definition 24.3. tmod: ti mer mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 sfr definition 24.4. tl0: timer 0 low byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 sfr definition 24.5. tl1: timer 1 low byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 sfr definition 24.6. th0: timer 0 hi gh byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 sfr definition 24.7. th1: timer 1 hi gh byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 sfr definition 24.8. tmr2cn: timer 2 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 sfr definition 24.9. tmr2rll: ti mer 2 reload register low byte . . . . . . . . . . . . . 201 sfr definition 24.10. tmr2 rlh: timer 2 reload re gister high byte . . . . . . . . . . . 201 sfr definition 24.11. tmr2l: timer 2 low byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 sfr definition 24.12. tmr2h timer 2 high byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 sfr definition 24.13. tmr3cn: timer 3 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 sfr definition 24.14. tmr3 rll: timer 3 reload regi ster low byte . . . . . . . . . . . . 207 sfr definition 24.15. tmr3 rlh: timer 3 reload re gister high byte . . . . . . . . . . . 207 sfr definition 24.16. tmr3l: timer 3 low byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 sfr definition 24.17. tmr3h timer 3 high byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 sfr definition 25.1. pca0cn: pca control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 sfr definition 25.2. pca0md: pca mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
rev. 0.2 15 c8051f336/7/8/9 sfr definition 25.3. pca0pwm: pc a pwm configuration . . . . . . . . . . . . . . . . . . . . 225 sfr definition 25.4. pc a0cpmn: pca capture/compare mode . . . . . . . . . . . . . . . 226 sfr definition 25.5. pca0l: pca counter/timer low byte . . . . . . . . . . . . . . . . . . . 227 sfr definition 25.6. pca0h: pca counter/timer high byte . . . . . . . . . . . . . . . . . . . 227 sfr definition 25.7. pca0cpln: pca capture module low byte . . . . . . . . . . . . . . . 228 sfr definition 25.8. pca0cphn: pca capture module high byte . . . . . . . . . . . . . . 228 c2 register definition 26.1. c2add: c2 address . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 c2 register definition 26.2. device id: c2 device id . . . . . . . . . . . . . . . . . . . . . . . . 230 c2 register definition 26.3. revid: c2 revision id . . . . . . . . . . . . . . . . . . . . . . . . . 230 c2 register definition 26.4. fp ctl: c2 flash programming cont rol . . . . . . . . . . . . 231 c2 register definition 26.5. fp dat: c2 flash programming data . . . . . . . . . . . . . . 231
c8051f336/7/8/9 16 rev. 0.2 1. system overview c8051f336/7/8/9 devices are fully integrated mixed-si gnal system-on-a-chip m cus. highlighted features are listed below. refer to ta b l e 2.1 for specific product feature selection and part ordering numbers. ? high-speed pipelined 8051-compatible microcontroller core (up to 25 mips) ? in-system, full-speed, non-intrusive debug interface (on-chip) ? true 10-bit 200 ksps 20-channel single-ended/diffe rential adc with analog multiplexer ? 10-bit current output dac ? precision programmable 24.5 mhz internal oscillator ? low-power, low-fr equency oscillator ? 16 kb of on-chip flash memory?512 bytes are reserved ? 768 bytes of on-chip ram ? smbus/i2c, enhanced uart, and enhanced spi serial interfaces implemented in hardware ? four general-purpose 16-bit timers ? programmable counter/timer array (pca) with three capture/compare modules and watchdog timer function ? on-chip power-on reset, v dd monitor, and temperature sensor ? on-chip voltage comparator ? 21 or 17 port i/o (5 v tolerant) ? low-power suspend mode with fast wake-up time with on-chip power-on reset, v dd monitor, watchdog timer, and cl ock oscillator, t he c8051f336/7/8/9 devices are truly stand-alone system-on-a-chip solu tions. the flash memory can be reprogrammed even in-circuit, providing non-vo latile data storage, and also allowing field upgrades of the 8051 firmware. user software has complete control of all peripherals, and ma y individually shut down any or all peripherals for power savings. the on-chip silicon labs 2- wire (c2) development interface allo ws non-intrusive (uses no on-chip resources), full speed, in-circuit debugging using the production mcu installed in the final application. this debug logic supports inspection and modification of memory and registers, setting breakpoints, single stepping, run and halt commands. all analog and digita l peripherals are fully functional while debugging using c2. the two c2 interface pins can be shared with user functions , allowing in-system debugging with - out occupying package pins. each device is specified for 2.7 to 3.6 v operation over the industrial temperature range (?40 to +85 c). the port i/o and rst pins are tolerant of input signals up to 5 v. the c8051f336/7 are available in a 20- pin qfn package and the c8051f338/9 are available in a 24-pin qfn package. both package options are lead-free and rohs compliant. see ta b l e 2.1 for ordering information. block diagrams are included in figure 1.1 and figure 1.2 .
port 0 drivers digital peripherals uart timers 0, 1, 2, 3 pca/ wdt smbus priority crossbar decoder p0.0/vref p0.1/ida0 p0.2/xtal1 p0.3/xtal2 p0.4/tx p0.5/rx p0.6/cnvstr p0.7 crossbar control port i/o configuration cip-51 8051 controller core 16k byte isp flash program memory 256 byte sram sfr bus 512 byte xram port 1 drivers p1.0 p1.1 p1.2 p1.3 p1.4 p1.5 port 2 drivers p2.0/c2d spi analog peripherals comparator + - power net vdd gnd xtal1 sysclk system clock configuration external oscillator circuit precision 24.5 mhz oscillator debug / programming hardware power on reset reset c2d c2ck/rst 10-bit 200 ksps adc a m u x temp sensor vref vdd vdd c8051f336 only xtal2 low-freq. oscillator 10-bit idac vref gnd p1.6 p1.7 ida0 cp0, cp0a rev. 0.2 17 c8051f336/7/8/9 figure 1.1. c8051f336/7 block diagram
port 0 drivers digital peripherals uart timers 0, 1, 2, 3 pca/ wdt smbus priority crossbar decoder p0.0/vref p0.1/ida0 p0.2/xtal1 p0.3/xtal2 p0.4/tx p0.5/rx p0.6/cnvstr p0.7 crossbar control port i/o configuration cip-51 8051 controller core 16 kb isp flash program memory 256 byte sram sfr bus 512 byte xram port 1 drivers p1.0 p1.1 p1.2 p1.3 p1.4 p1.5 port 2 drivers p2.0 p2.1 p2.2 p2.3 p2.4/c2d spi analog peripherals comparator + - power net vdd gnd xtal1 sysclk system clock configuration external oscillator circuit precision 24.5 mhz oscillator debug / programming hardware power on reset reset c2d c2ck/rst 10-bit 200 ksps adc a m u x temp sensor vref vdd vdd c8051f338 only xtal2 low-freq. oscillator 10-bit idac vref gnd p1.6 p1.7 ida0 cp0, cp0a c8051f336/7/8/9 18 rev. 0.2 figure 1.2. c8051f338/9 block diagram
rev. 0.2 19 c8051f336/7/8/9 1.1. cip-51? microcontroller core 1.1.1. fully 8051 compatible the c8051f336/7/8/9 family utilizes silicon labs' proprietary cip-51 microcontroller core. the cip-51 is fully compatible with the mcs-51? instruction set; standard 803x/805x assemblers and compilers can be used to develop software. the cip-51 core offers all the peripherals included with a standard 8052, includ - ing four 16-bit counter/timers, a full-duplex uart wit h extended baud rate configuration, an enhanced spi port, 768 bytes of internal ram, 128 byte special function register (sfr) address space, and 17 or 21 i/o pins. 1.1.2. improved throughput the cip-51 employs a pipelined architecture that grea tly increases its instruction throughput over the stan - dard 8051 architecture. in a standar d 8051, all instructions except for mul and div take 12 or 24 system clock cycles to execute with a ma ximum system clock of 12-to-24 mhz. by contrast, the cip-51 core exe - cutes 70% of its instructions in one or two system clock cycles, with only four inst ructions taking more than four system clock cycles. the cip-51 has a total of 109 instructions. the table below shows the total number of instructions that require each execution time. clocks to execute 1 2 2/3 3 3/4 4 4/5 5 8 number of instructions 26 50 5 14 7 3 1 2 1 with the cip-51's maximum system clock at 25 mhz, it has a peak throughput of 25 mips. 1.1.3. additional features the c8051f336/7/8/9 soc family includes several key enhancements to the cip-51 core and peripherals to improve performance and ease of use in end applications. the extended interrupt handler provides multiple interrupt sources into the cip-51 allowing numerous ana - log and digital peripherals to interrupt the controller. an interrupt driven system requires less intervention by the mcu, giving it more effective throughput. the extra interrupt sources are very useful when building multi-tasking, real-time systems. eight reset sources are available: power-on reset circuitry (por), an on-chip v dd monitor (forces reset when power supply voltage drops be low safe levels), a watchdog time r, a missing clock detector, a volt - age level detection from comparator0, a forced softwa re reset, an external reset pin, and an illegal flash access protection circuit. each rese t source except for the por, reset input pin, or flash error may be disabled by the user in software. the wdt may be permanently enabled in software after a power-on reset during mcu initialization. the internal oscillator is factory calibrated to 24.5 mhz and is accurate to 2% over the full temperature and supply range. the internal osc illator period can also be adjusted by user firmwa re. an additional low- frequency oscillator is also available which facilitates low-power operation. an ex ternal oscillator drive cir - cuit is included, allowing an external crystal, cerami c resonator, capacitor, rc, or cmos clock source to generate the system clock. if desired, the system cloc k source may be switched on-the-fly between both internal and external oscillator circ uits. an external oscilla tor can also be extremely useful in low power applications, allowing the mcu to run from a slow (pow er saving) source, while pe riodically switching to the fast (up to 25 mhz) internal oscillator as needed.
pca wdt missing clock detector (one- shot) (software reset) system reset reset funnel px.x px.x en swrsf internal oscillator system clock cip-51 microcontroller core extended interrupt handler clock select en wdt enable mcd enable xtal1 xtal2 external oscillator drive errant flash operation /rst (wired-or) power on reset '0' + - comparator 0 c0rsef vdd + - supply monitor enable low frequency oscillator c8051f336/7/8/9 20 rev. 0.2 figure 1.3. on-chi p clock and reset 1.2. on-chip memory the cip-51 has a standard 8051 program and data addr ess configuration. it in cludes 256 bytes of data ram, with the upper 128 bytes dual-mapped. indirect addressing accesses the upper 128 bytes of general purpose ram, and direct addressing accesses the 128 byte sfr addre ss space. the lower 128 bytes of ram are accessible via direct and indirect addressing. the first 32 bytes are addressable as four banks of general purpose registers, and the next 16 byte s can be byte addressable or bit addressable. program memory consists of 16 kb of flash. this memory may be reprogrammed in-system in 512 byte sectors, and requires no special off-chip programming voltage. see figure 1.4 for the mcu system mem - ory map.
program/data memory (flash) (direct and indirect addressing) 0x00 0x7f upper 128 ram (indirect addressing only) 0x80 0xff special function register's (direct addressing only) data memory (ram) general purpose registers 0x1f 0x20 0x2f bit addressable lower 128 ram (direct and indirect addressing) 0x30 internal data address space external data address space xram - 512 bytes (accessable using movx instruction) 0x0000 0x01ff same 512 bytes as from 0x0000 to 0x01ff, wrapped on 512-byte boundaries 0x0200 0xffff 16 kb flash (in-system programmable in 512 byte sectors) 0x0000 reserved 0x3e00 0x3dff rev. 0.2 21 c8051f336/7/8/9 figure 1.4. on-chip memory map 1.3. on-chip debug circuitry the c8051f336/7/8/ 9 devices include on-chip silicon labs 2-wire (c2) debug circuitry that provides non- intrusive, full speed, in-circuit debugging of the production part installed in the end application. silicon labs' debugging syst em supports inspection and modificati on of memory and registers, break - points, and single stepping. no additional target ram, program memory, timers, or communications chan - nels are required. all the digital and analog periphera ls are functional and work correctly while debugging. all the peripherals (except for the adc and smbus) are stalled when the mcu is halted, during single stepping, or at a breakpoint in order to keep them synchronized. the c8051f336dk development kit provides all the har dware and software necessary to develop applica - tion code and perform in-circuit debugging with the c8051f336/7/8/9 mcus. the kit includes software with a developer's studio and debugger, evaluation compiler and assembler, and a debug adapter. it also has a target application board with the associated mcu insta lled and prototyping area, plus the required cables, and power supply. the ide software requires a pc running a wind ows operating system. the silicon labs ide interface is a vastly superior developing and debu gging configuratio n, compared to standard mcu emulators that use on-board "ice chips" and require the mcu in the application board to
c8051f336/7/8/9 22 rev. 0.2 be socketed. silicon labs' debug para digm increases ease of use and preserves the performance of the precision analog peripherals. 1.4. programmable digital i/o and crossbar c8051f338/9 devices include 21 i/o pins (two byte-wide ports and one 5-bit-wide port). c8051f336/7 devices include 17 i/o pins (two byte-wide ports an d one 5-bit-wide port). the c8051f336/7/8/9 ports behave like typical 8051 ports with a few enhancements. each port pin may be configured as an analog input or a digital i/o pin. pins selected as digital i/o s may additionally be configured for push-pull or open- drain output. the ?weak pullups? that are fixed on typica l 8051 devices may be globally disabled, providing power saving capabilities. the digital crossbar allows mapping of internal digi tal system resources to port i/o pins. (see figure 1.5.) on-chip counter/timers, serial buses, hw interrupts, comparator output, and other digital signals in the controller can be configured to appear on the port i/o pins specified in the crossbar control registers. this allows the user to select the exact mix of general purpose port i/o and digital resources needed for the particular application. xbr0, xbr1, pnskip registers digital crossbar priority decoder 2 p0 i/o cells p0.0 p0.7 8 pnmdout, pnmdin registers uart (internal digital signals) highest priority lowest priority sysclk 2 smbus t0, t1 2 4 pca 4 spi cp0 outputs 2 p1 i/o cells p1.0 p1.7 8 (port latches) p0 (p0.0-p0.7) (p1.0-p1.7) 8 8 p1 (p2.0-p2.3*) 4 p2 *p2.1-p2.3 only available on qfn24 packages p2 i/o cells p2.0 p2.3* 4 figure 1.5. digital crossbar diagram
rev. 0.2 23 c8051f336/7/8/9 1.5. serial ports the c8051f336/7/8/9 family includes an smbus/i 2 c interface, a full-duplex uart with enhanced baud rate configuration, and an enhanced spi interface. ea ch of the serial buses is fully implemented in hard - ware and makes extensive use of t he cip-51's interrupts, thus requiring very little cpu intervention. 1.6. programmable counter array an on-chip programmable counter/timer array (pca) is included in addition to the four 16-bit general pur - pose counter/timers. the pca consists of a dedicated 16-bit counter/timer time base with three program - mable capture/compare modules. the pca clock is de rived from one of six so urces: the system clock divided by 12, the system clock divided by 4, timer 0 overflows, an external cl ock input (eci), the system clock, or the external osc illator clock source divided by 8. the extern al clock source selection is useful for real-time clock functi onality, where the pca is clocked by an exte rnal source while the internal oscillator drives the system clock. each capture/compare module can be configured to operate in a variety of modes: edge-triggered cap - ture, software timer, high speed output, pulse width modulator (8, 9, 10, 11, or 16-bit), or frequency output. additionally, capture/comp are module 2 offers watchdog timer (wdt) ca pabilities. following a system reset, module 2 is configured and enabled in wdt mode. the pca capture/compare module i/o and external clock input may be routed to port i/o via the digital crossbar. 16-bit counter/timer cex1 eci digital crossbar cex2 cex0 port i/o capture/compare module 1 capture/compare module 0 capture/compare module 2 pca clock mux sysclk/12 sysclk/4 timer 0 overflow eci sysclk external clock/8 figure 1.7. pc a block diagram
c8051f336/7/8/9 24 rev. 0.2 1.7. 10-bit analog to digital converter the c8051f336/8 devices include an on-chip 10-bit sar adc with a differential in put multiplexer. with a maximum throughput of 200 ksps, the adc offers true 10-bit linearity with an inl and dnl of 1 lsb. the adc system includes a configurable analog multiple xer that selects both positive and negative adc inputs. up to twenty port i/o pins are available as an adc inputs; additionally, the on-chip temperature sensor output and the power supply voltage (v dd ) are available as adc inputs. user firmware may shut down the adc to save power. conversions can be started in six ways: a software comma nd, an overflow of timer 0, 1, 2, or 3, or an external convert start signal. this flexibility allows the start of conver sion to be triggered by software events, a periodic signal (timer overflows), or extern al hw signals. conversion completions are indicated by a status bit and an interrupt (if enabled). the resu lting 10-bit data word is latched into the adc data sfrs upon completion of a conversion. window compare registers for the adc data can be conf igured to interrupt the co ntroller when adc data is either within or outside of a specified range. the adc can monitor a key voltage continuously in back - ground mode, but not interrupt the controller unless the converted data is within/outside the specified range. 10-bit sar adc timer 1 overflow cnvstr input timer 3 overflow (+) (-) configuration, control, and data registers amux temp sensor amux vdd p0.0 p2.3 vref analog multiplexer timer 0 overflow timer 2 overflow start conversion 000 ad0busy (w) 001 010 011 100 101 16 window compare logic window compare interrupt adc data registers end of conversion interrupt gnd p0.0 p2.3 figure 1.8. 10-bit adc block diagram
rev. 0.2 25 c8051f336/7/8/9 1.8. comparator c8051f336/7/8/9 devices include an on-chip voltage comparator that is enabled/disabled and configured via user software. port i/o pins may be configured as comparator inputs via a selection mux. two compar - ator outputs may be routed to a port pin if desired: a latched output and/or an unlatched (asynchronous) output. comparator response time is programmable, allowing the user to select between high-speed and low-power modes. positive and negative hysteresis are also configurable. comparator interrupts may be generated on rising, fallin g, or both edges. when in idle mode, these inter - rupts may be used as a ?wake-up? source. comparator0 may also be configured as a reset source. figure 1.9 shows the comparator0 block diagram. vdd reset decision tree + - crossbar q q set clr d q q set clr d (synchronizer) gnd cpt0md cp0rie cp0fie cp0md1 cp0md0 cp0 cp0a cp0 interrupt 0 1 0 1 cp0rif cp0fif 0 1 cp0en 0 1 ea cpt0cn cp0en cp0out cp0rif cp0fif cp0hyp1 cp0hyp0 cp0hyn1 cp0hyn0 cp0 + p0.0 cp0 - cpt0mx cmx0n3 cmx0n2 cmx0n1 cmx0n0 cmx0p3 cmx0p2 cmx0p1 cmx0p0 p0.2 p0.4 p0.6 p1.0 p1.2 p1.4 p1.6 p2.0 p2.2 p0.1 p0.3 p0.5 p0.7 p1.1 p1.3 p1.5 p1.7 p2.1 p2.3 figure 1.9. comparator0 block diagram
c8051f336/7/8/9 26 rev. 0.2 1.9. 10-bit current output dac the c8051f336/8 devices include a 10-bit current -mode digital-to-analog converter (ida0). the maxi - mum current output of the ida0 can be adjusted for three different current settings; 0.5 ma, 1 ma, and 2 ma. ida0 features a flexible output update mechani sm which allows for seamless full-scale changes and supports jitter-free updates for waveform generation. three update modes are provided, allowing ida0 output updates on a write to ida0h, on a timer overflow, or on an external pin edge. ida0 10 ida0 ida0cn ida0en ida0cm2 ida0cm1 ida0cm0 ida0omd1 ida0omd0 ida0h ida0l latch 8 2 ida0h timer 0 timer 1 timer 2 timer 3 cnvstr figure 1.10. ida0 functional block diagram
rev. 0.2 27 c8051f336/7/8/9 2. ordering information table 2.1. product selection guide ordering part number mips (peak) flash memory (kb) ram (bytes) calibrated internal 24.5 mhz oscillator internal 80 khz oscillator smbus/i 2 c enhanced spi uart timers (16-bit) rtc operation programmable counter array digital port i/os 10-bit 200ksps adc 10-bit current output dac internal voltage reference temperature sensor analog comparator lead-free (rohs compliant) package C8051F336-GM 25 16 768 3 3 3 3 3 4 3 3 17 3 3 3 3 3 3 qfn-20 c8051f337-gm 25 16 768 3 3 3 3 3 4 3 3 17 ? ? ? ? 3 3 qfn-20 c8051f338-gm 25 16 768 3 3 3 3 3 4 3 3 21 3 3 3 3 3 3 qfn-24 c8051f339-gm 25 16 768 3 3 3 3 3 4 3 3 21 ? ? ? ? 3 3 qfn-24
c8051f336/7/8/9 28 rev. 0.2 3. pin definitions table 3.1. pin definitions fo r the c8051f336/7/8/9 name pin ?f336/7 pin ?f338/9 type description v dd 3 4 power supply voltage. gnd 2 3 ground. note: this ground connection is required. the center pad may optionally be connected to ground also. rst / c2ck 4 5 d i/o d i/o device reset. open-drain output of internal por or v dd monitor. an external source ca n initiate a system reset by driving this pin low for at least 10 s. clock signal for the c2 debug interface. p2.0/ c2d 5 d i/o d i/o port 2.0. bi-directional data signal for the c2 debug interface. p2.4/ c2d 6 d i/o d i/o port 2.4. bi-directional data signal for the c2 debug interface. p0.0/ vref 1 2 d i/o or a in a in port 0.0. external vref input. p0.1 ida0 20 1 d i/o or a in aout port 0.1. ida0 output. p0.2/ xtal1 19 24 d i/o or a in a in port 0.2. external clock input. this pi n is the external oscillator return for a crystal or resonator. p0.3/ xtal2 18 23 d i/o or a in a i/o or d in port 0.3. external clock output. for an ex ternal crystal or resonator, this pin is the excitation driver. this pin is the external clock input for cmos, capacitor, or rc oscillator configurations. p0.4 17 22 d i/o or a in port 0.4.
rev. 0.2 29 c8051f336/7/8/9 p0.5 16 21 d i/o or a in port 0.5. p0.6/ cnvstr 15 20 d i/o or a in d in port 0.6. adc0 external convert start or ida0 update source input. p0.7 14 19 d i/o or a in port 0.7. p1.0 13 18 d i/o or a in port 1.0. p1.1 12 17 d i/o or a in port 1.1. p1.2 11 16 d i/o or a in port 1.2. p1.3 10 15 d i/o or a in port 1.3. p1.4 9 14 d i/o or a in port 1.4. p1.5 8 13 d i/o or a in port 1.5. p1.6 7 12 d i/o or a in port 1.6. p1.7 6 11 d i/o or a in port 1.7. p2.0 5 10 d i/o or a in port 2.0. p2.1 9 d i/o or a in port 2.1. p2.2 8 d i/o or a in port 2.2. p2.3 7 d i/o or a in port 2.3. table 3.1. pin definitions fo r the c8051f336/7/8/9 (continued) name pin ?f336/7 pin ?f338/9 type description
3 4 5 1 2 8 9 10 6 7 13 12 11 15 14 18 19 20 16 17 p0.0 gnd vdd /rst/c2ck p2.0/c2d p1.7 p1.6 p1.5 p1.4 p1.3 p1.2 p1.1 p1.0 p0.7 p0.6 p0.5 p0.4 p0.3 p0.2 p0.1 c8051f336/7 top view gnd (optional) c8051f336/7/8/9 30 rev. 0.2 figure 3.1. qfn-20 pino ut diagram (top view)
3 4 5 1 2 9 10 11 7 8 16 15 14 18 17 22 23 24 20 21 p0.0 gnd vdd /rst/c2ck p2.4/c2d p1.7 p1.6 p2.3 p2.2 p2.1 p1.2 p1.1 p1.0 p1.5 p1.4 p0.5 p0.4 p0.3 p0.2 p0.7 c8051f338/9 top view 6 12 p2.0 13 p1.3 19 p0.6 p0.1 gnd (optional) rev. 0.2 31 c8051f336/7/8/9 figure 3.2. qfn-24 pino ut diagram (top view)
c8051f336/7/8/9 32 rev. 0.2 4. qfn-20 package specifications table 4.1. qfn-20 package dimensions dimension min typ max dimension min typ max notes: 1. all dimensions shown are in millim eters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to the jedec solid state outline mo-220, variation vggd except for custom features d2, e2, and l which are toleranced per supplier designation. 4. recommended card reflow profile is per the je dec/ipc j-std-020c specification for small body components. figure 4.1. qfn-20 package drawing a 0.80 0.90 1.00 e2 2.05 2.15 2.25 a1 0.00 0.02 0.05 l 0.30 0.40 0.50 b 0.18 0.25 0.30 l1 0.00 ? 0.15 d 4.00 bsc. aaa ? ? 0.15 d2 2.05 2.15 2.25 bbb ? ? 0.10 e 0.50 bsc. ddd ? ? 0.05 e 4.00 bsc. eee ? ? 0.08
rev. 0.2 33 c8051f336/7/8/9 5. qfn-24 package specifications table 5.1. qfn-24 package dimensions dimension min typ max dimension min typ max a 0.70 0.75 0.80 e2 2.60 2.70 2.80 a1 0.00 0.02 0.05 l 0.35 0.40 0.45 b 0.18 0.25 0.30 l1 0.00 ? 0.15 d 4.00 bsc. aaa ? ? 0.15 d2 2.60 2.70 2.80 bbb ? ? 0.10 e 0.50 bsc. ccc ? ? 0.05 e 4.00 bsc. ddd ? ? 0.08 notes: 1. all dimensions shown are in millim eters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to jedec solid state outline mo-220, variation wggd except for custom features d2, e2, and l which are toleranced per supplier designation. 4. recommended card reflow profile is per the je dec/ipc j-std-020c specification for small body components. figure 5.1. qfn-24 package drawing
c8051f336/7/8/9 34 rev. 0.2 6. electrical characteristics 6.1. absolute maximum specifications table 6.1. absolute maximum ratings note: stresses above those listed under ?absolute maximum ra tings? may cause permanent damage to the device. this is a stress rating only and functional operation of the devices at those or any other conditions above those indicated in the operation list ings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. parameter conditions min typ max units ambient temperature under bias ?55 ? 125 c storage temperature ?65 ? 150 c voltage on any port i/o pin or rst with respect to gnd ?0.3 ? 5.8 v voltage on v dd with respect to gnd ?0.3 ? 4.2 v maximum total current through v dd or gnd ? ? 500 ma maximum output current sunk by rst or any port pin ??100ma
rev. 0.2 35 c8051f336/7/8/9 6.2. electrical characteristics table 6.2. global electrical characteristics ?40 to +85 c, 25 mhz system clock unless otherwise specified. parameter conditions min typ max units digital supply voltage normal operation v rst 1 3.0 3.6 v writing or erasing flash memory 2.7 3.0 3.6 v digital supply ram data retention voltage ?1.5? v sysclk (system clock) (note 2) 0?25mhz t sysh (sysclk high time) 18 ? ? ns t sysl (sysclk low time) 18 ? ? ns specified operating temperature range ?40 ? +85 c digital supply current?cpu active (normal mode, fetching instructions from flash) i dd (note 3) v dd = 3.6 v, f = 25 mhz ? 12.3 tbd ma v dd = 3.0 v, f = 25 mhz ? 8.9 tbd ma v dd = 3.0 v, f = 1 mhz ? 0.46 ? ma v dd = 3.0 v, f = 80 khz ? 40 ? a i dd supply sensitivity (note 3) f = 25 mhz ? tbd ? %/v f = 1 mhz ? tbd ? %/v i dd frequency sensitivity (note 3, note 4) v dd = 3.0 v, f < 15 mhz, t = 25 c?tbd?ma/mhz v dd = 3.0 v, f > 15 mhz, t = 25 c?tbd?ma/mhz v dd = 3.6 v, f < 15 mhz, t = 25 c?tbd?ma/mhz v dd = 3.6 v, f > 15 mhz, t = 25 c?tbd?ma/mhz digital supply current?cpu inactive (idle mode , not fetching instructions from flash) i dd (note 3) v dd = 3.6 v, f = 25 mhz ? 6.0 tbd ma v dd = 3.0 v, f = 25 mhz ? 4.4 tbd ma v dd = 3.0 v, f = 1 mhz ? 0.2 ? ma v dd = 3.0 v, f = 80 khz ? 16 ? a
c8051f336/7/8/9 36 rev. 0.2 i dd supply sensitivity (note 3) f = 25 mhz ? tbd ? %/v f = 1 mhz ? tbd ? %/v i dd frequency sensitivity (note 3, note 5) v dd = 3.0 v, f < 1 mhz, t = 25 c?tbd?ma/mhz v dd = 3.0 v, f > 1 mhz, t = 25 c?tbd?ma/mhz v dd = 3.6 v, f < 1 mhz, t = 25 c?tbd?ma/mhz v dd = 3.6 v, f > 1 mhz, t = 25 c?tbd?ma/mhz digital supply current (stop or suspend mode, shut- down) oscillator not running, v dd monitor disabled ?< 0.1? a notes: 1. given in table 6.4 on page 37 . 2. sysclk must be at least 32 khz to enable debugging. 3. based on device characterization data; not production tested. 4. idd can be estimated for frequencies <= 15 mhz by simply multiplying the frequency of interest by the frequency sensitivity number for that range . when using these numbers to estimate i dd for >15 mhz, the estimate should be the current at 25 mhz minus the difference in current indicated by the frequency sensitivity number. for example: v dd = 3.0 v; f = 20 mhz, i dd = 7.8 ma - (25 mhz - 20 mhz) * 0.21 ma/mhz = 6.75 ma. 5. idle idd can be estimated for frequencies <= 1 mhz by simply multiplying the frequency of interest by the frequency sensitivity number fo r that range. when using these numbers to estimate idle i dd for >1 mhz, the estimate should be the current at 25 mhz minus the difference in current indicated by the frequency sensitivity number. for example: v dd = 3.0 v; f = 5 mhz, idle i dd = 4.8 ma - (25 mhz - 5 mhz) * 0.15 ma/mhz = 1.8 ma. table 6.3. port i/o dc electri cal characteristics v dd = 2.7 to 3.6 v, ?40 to +85 c unless otherwise specified. parameters conditions min typ max units output high voltage i oh = ?3 ma, port i/o push-pull i oh = ?10 a, port i/o push-pull i oh = ?10 ma, port i/o push-pull v dd ? 0.7 v dd ? 0.1 ? ? ? v dd ? 0.8 ? ? ? v output low voltage i ol = 8.5 ma i ol = 10 a i ol = 25 ma ? ? ? ? ? 1.0 0.6 0.1 ? v input high voltage 2.0 ? ? v input low voltage ? ? 0.8 v input leakage current weak pullup off weak pullup on, v in = 0 v ? ? ? 50 1 100 a table 6.2. global electrical characteristics (continued) ?40 to +85 c, 25 mhz system clock unless otherwise specified. parameter conditions min typ max units
table 6.4. reset electrical characteristics ?40 to +85 c unless otherwise specified. table 6.5. flash electrical characteristics v dd = 2.7 to 3.6 v; ? 40 to +85 oc unless otherwise specified. *note: 512 bytes at addresses 0x3e00 to 0x3fff are reserved. rev. 0.2 37 c8051f336/7/8/9 parameter conditions min typ max units rst output low voltage i ol = 8.5 ma, v dd = 2.7 v to 3.6 v ??0.6v rst input low voltage ? ? 0.6 rst input pullup current rst = 0.0 v ? 50 100 a v dd por threshold (v rst ) 2.40 2.55 2.70 v missing clock detector time- out time from last system clock rising edge to reset initiation 100 220 600 s reset time delay delay between release of any reset source and code execution at location 0x0000 ??40s minimum rst low time to generate a system reset 15 ? ? s v dd monitor turn-on time 100 ? ? s v dd monitor supply current ?2040a parameter conditions min typ max units flash size 16384 * ?? bytes endurance 20 k 100 k ? erase/write erase cycle time 25 mhz system clock 10 15 20 ms write cycle time 25 mhz system clock 40 55 70 s
table 6.6. internal high-frequency oscill ator electrical characteristics v dd = 2.7 to 3.6 v; t a = ?40 to +85 c unless otherwise specified; us ing factory-calibrated settings. oscillator frequency ifcn = 11b 24 24.5 25 mhz oscillator supply current (from v dd ) 25 c, v dd = 3.0 v, oscicn.7 = 1, ocsicn.5 = 0 ? 450 600 a power supply sensitivity constant temperature ? 0.12 ? %/v temperature sensitivity constant supply ? 60 ? ppm/c table 6.7. internal low-frequency oscill ator electrical characteristics v dd = 2.7 to 3.6 v; t a = ?40 to +85 c unless otherwise specified; us ing factory-calibrated settings. oscillator frequency oscld = 11b 72 80 88 khz oscillator supply current (from v dd ) 25 c, v dd = 3.0 v, osclcn.7 = 1 ? 5.5 10 a power supply sensitivity constant temperature ? 2.4 ? %/v temperature sensitivity constant supply ? 30 ? ppm/c c8051f336/7/8/9 38 rev. 0.2 parameter conditions min typ max units parameter conditions min typ max units
table 6.8. adc0 electrical characteristics v dd = 3.0 v, vref = 2.40 v (refsl=0), ? 40 to +85 c unless otherwise specified. parameter conditions min typ max units dc accuracy resolution 10 bits integral nonlinearity ? 0.5 1 lsb differential nonlinearity guaranteed monotonic ? 0.5 1 lsb offset error ?12 3 12 lsb full scale error ?5 1 5 lsb offset temperature coefficient ? 3 ? ppm/c dynamic perf ormance (10 khz sine-wave single-ended input, 1 db below full scale, 200 ksps) signal-to-noise plus distortion 53 58 ? db total harmonic distortion up to the 5th harmonic ? ?75 ? db spurious-free dynamic range ? 75 ? db conversion rate sar conversion clock ? ? 3.125 mhz conversion time in sar clocks 13 ? ? clocks track/hold acquisition time 300 ? ? ns throughput rate ? ? 200 ksps analog inputs adc input voltage range single ended (ain+ ? gnd) differential (ain+ ? ain?) 0 ?vref ? vref vref v v absolute pin voltage with respect to gnd single ended or differential 0 ? v dd v sampling capacitance ? 5 ? pf input multiplexer impedance ? 5 ? k ? power supply current (v dd supplied to adc0) operating mode, 200 ksps ? 500 900 a power supply rejection ? 3 ? mv/v *note: represents one standard deviation from the mean. rev. 0.2 39 c8051f336/7/8/9
table 6.9. temperature sensor elec trical characteristics v dd = 3.0 v, ? 40 to +85 c unless otherwise specified. parameter conditions min typ max units linearity ? 0.2 ? c relative accuracy ? tbd ? c slope ? tbd ? mv/c slope error* ? tbd ? v/c offset te m p = 0 c ? tbd ? mv offset error* te m p = 0 c ? tbd ? mv power supply current ? tbd ? a *note: represents one standard deviation from the mean. table 6.10. voltage reference elect rical characteristics v dd = 3.0 v; ?40 to +85 c unless otherwise specified. parameter conditions min typ max units internal reference (refbe = 1) output voltage 25 c ambient 2.35 2.42 2.50 v vref short-circuit current ? ? 10 ma vref temperature coefficient ? 30 ? ppm/c load regulation load = 0 to 200 a to agnd ? 3 ? v/a vref turn-on time 1 4.7 f tantalum, 0.1 f ceramic bypass ? 7.5 ? ms vref turn-on time 2 0.1 f ceramic bypass ? 200 ? s power supply rejection ? ?0.6 ? mv/v external reference (refbe = 0) input voltage range 0 ? v dd v input current sample rate = 200 ksps; vref = 3.0 v ? tbd ? a power specifications reference bias generator refbe = ?1? or tempe = ?1? or ida0en = ?1? ? 30 50 a c8051f336/7/8/9 40 rev. 0.2
table 6.11. idac electrical characteristics ? 40 to +85 c, v dd = 3.0 v full-scale output current set to 2 ma unless otherwise specified. parameter conditions min typ max units static performance resolution 10 bits integral nonlinearity ? 0.5 2 lsb differential nonlinearity guaranteed monotonic ? 0.5 1 lsb output compliance range ? ? v dd ? 1.2 v offset error ? 0 ? a full scale error 2 ma full scale output current ? 0 30 a full scale error tempco ? 30 ? ppm/c v dd power supply rejection ratio ? 6 ? a/v dynamic performance output settling time to 1/2 lsb ida0h:l = 0x3ff to 0x000 ? 5 ? s startup time ? 5 ? s gain variation 1 ma full scale output current 0.5 ma full scale output current ? ? 1 1 ? ? % % power consumption power supply current (v dd supplied to idac) 2 ma full scale output current 1 ma full scale output current 0.5 ma full scale output current ? ? ? 2100 1100 600 ? ? ? a a a rev. 0.2 41 c8051f336/7/8/9
table 6.12. comparator electri cal characteristics v dd = 3.0 v, ?40 to +85 c unless otherwise noted. parameter conditions min typ max units response time: mode 0, vcm * = 1.5 v cp0+ ? cp0? = 100 mv ? 100 ? ns cp0+ ? cp0? = ?100 mv ? 200 ? ns response time: mode 1, vcm * = 1.5 v cp0+ ? cp0? = 100 mv ? 250 ? ns cp0+ ? cp0? = ?100 mv ? 350 ? ns response time: mode 2, vcm * = 1.5 v cp0+ ? cp0? = 100 mv ? 400 ? ns cp0+ ? cp0? = ?100 mv ? 800 ? ns response time: mode 3, vcm * = 1.5 v cp0+ ? cp0? = 100 mv ? 1100 ? ns cp0+ ? cp0? = ?100 mv ? 5000 ? ns common-mode rejection ratio ? 1.25 5 mv/v positive hysteresis 1 cp0hyp1?0 = 00 ? 0 1 mv positive hysteresis 2 cp0hyp1?0 = 01 1 5 10 mv positive hysteresis 3 cp0hyp1?0 = 10 6 10 20 mv positive hysteresis 4 cp0hyp1?0 = 11 12 20 30 mv negative hysteresis 1 cp0hyn1?0 = 00 0 1 mv negative hysteresis 2 cp0hyn1?0 = 01 1 5 10 mv negative hysteresis 3 cp0hyn1?0 = 10 6 10 20 mv negative hysteresis 4 cp0hyn1?0 = 11 12 20 30 mv inverting or non- inverting input voltage range ?0.25 ? v dd + 0.25 v input capacitance ? 4 ? pf input bias current ? 0.001 ? na input offset voltage ?5 ? +5 mv power supply power supply rejection ? 0.1 ? mv/v power-up time ? 10 ? s supply current at dc mode 0 ? 10 20 a mode 1 ? 4 10 a mode 2 ? 2 5 a mode 3 ? 0.4 2.5 a *note: vcm is the common-mode voltage on cp0+ and cp0?. c8051f336/7/8/9 42 rev. 0.2
rev. 0.2 43 c8051f336/7/8/9 7. 10-bit adc (adc0, c8051f336/8 only) the adc0 on the c8051f336/8 is a 200 ksps, 10-bit successive-approxi mation-register (sar) adc with integrated track-and-hold and programmable window de tector. the adc is fully configurable under soft - ware control via special function registers. the adc0 operates in both single-ended and differential modes, and may be configured to measure various diff erent signals using the analog multiplexer described in section ?7.4. adc0 analog multiplexer (c8051f336/8 only)? on page 55 . the voltage reference for the adc is selected as described in section ?8. temperature sensor (c8051f336/8 only)? on page 58 . the adc0 subsystem is enabled only when the ad0en bit in the adc0 control regist er (adc0cn) is set to logic 1. the adc0 subsystem is in low powe r shutdown when this bit is logic 0. adc0cf ad0ljst ad0sc0 ad0sc1 ad0sc2 ad0sc3 ad0sc4 10-bit sar adc ref sysclk adc0h 32 adc0cn ad0cm0 ad0cm1 ad0cm2 ad0wint ad0busy ad0int ad0tm ad0en timer 0 overflow timer 2 overflow timer 1 overflow start conversion 000 ad0busy (w) vdd adc0lth ad0wint 001 010 011 100 cnvstr input window compare logic 101 timer 3 overflow adc0ltl adc0gth adc0gtl adc0l ain+ ain- from amux0 figure 7.1. adc0 functional block diagram
c8051f336/7/8/9 44 rev. 0.2 7.1. output code formatting the adc is in single-ended mode wh en the negative input is connected to gnd. the adc will be in differ - ential mode when the negative input is connected to any other option. the output code format differs between single-ended and differential modes. the registers adc0h and adc0l contain the high and low bytes of the output conversion code from the adc at the completion of each conversion. data can be right- justified or left-justified, depending on the setting of the ad0ljst. when in single-ended mode, conversion codes are represented as 10-bit unsigned integers. inputs are measured from ?0? to vref x 1023/1024. example codes are shown below for both right-justified and left-justified data. unused bits in the adc0h and adc0l registers are set to ?0?. when in differential mode, conversion codes are represented as 10-bit signed 2?s complement numbers. inputs are measured from ? vref to vref x 511/512. example codes are shown below for both right-jus - tified and left-justified data. for right-justified data, the unused msbs of adc0h are a sign-extension of the data word. for left-justified data, the unused lsbs in the adc0l register are set to ?0?. 7.2. modes of operation adc0 has a maximum conversion speed of 200 ksps. the adc0 conversion clock is a divided version of the system clock, determined by the ad0sc bits in the adc0cf register. 7.2.1. starting a conversion a conversion can be initiated in one of six ways, depending on the programmed states of the adc0 start of conversion mode bits (ad0cm2 ? 0) in register adc0cn. conversions may be initiated by one of the fol - lowing: 1. writing a ?1? to the ad0busy bit of register adc0cn 2. a timer 0 overflow (i.e., timed continuous conversions) 3. a timer 2 overflow 4. a timer 1 overflow 5. a rising edge on the cnvstr input signal (pin p0.6) 6. a timer 3 overflow writing a ?1? to ad0busy provides software contro l of adc0 whereby conversions are performed "on- demand". during conversion, the ad0busy bit is set to logic 1 and reset to logic 0 when the conversion is complete. the falling edge of ad0bu sy triggers an interrupt (when enabl ed) and sets the adc0 interrupt input voltage right-justified adc0h:adc0l (ad0ljst = 0) left-justified adc0h:adc0l (ad0ljst = 1) vref x 1023/1024 0x03ff 0xffc0 vref x 512/1024 0x0200 0x8000 vref x 256/1024 0x0100 0x4000 0 0x0000 0x0000 input voltage right-jus tified adc0h:adc0l (ad0ljst = 0) left-justified adc0h:adc0l (ad0ljst = 1) vref x 511/512 0x01ff 0x7fc0 vref x 256/512 0x0100 0x4000 0 0x0000 0x0000 ?vref x 256/512 0xff00 0xc000 ?vref 0xfe00 0x8000
rev. 0.2 45 c8051f336/7/8/9 flag (ad0int). note: when polling for adc conversion completions, the adc0 in terrupt flag (ad0int) should be used. converted data is available in th e adc0 data registers, adc0h:adc0l, when bit ad0int is logic 1. note that when timer 2 or timer 3 overflows are used as the co nversion source, low byte over - flows are used if timer 2/3 is in 8-bit mode; high by te overflows are used if timer 2/3 is in 16-bit mode. see section ?24. timers? on page 187 for timer configuration. important note about using cnvstr: the cnvstr input pin also functions as port pin p0.6. when the cnvstr input is used as the adc0 conversion source, port pin p0.6 should be skipped by the digital crossbar. to configure the crossbar to skip p0 .6, set to ?1? bit6 in register p0skip. see section ?20. port input/output? on page 126 for details on port i/o configuration. 7.2.2. tracking modes each adc0 conversion must be preceded by a minimum tracking time in order for the converted result to be accurate. the minimum tracking time is given in ta b l e 6.8 . the ad0tm bit in register adc0cn controls the adc0 track-and-hold mode. in its default state, the adc0 input is continuously tracked, except when a conversion is in progress. when the ad0tm bit is logic 1, adc0 operates in low-power track-and-hold mode. in this mode, each conversion is preceded by a tracking period of 3 sar clocks (after the start-of- conversion signal). when the cnvstr signal is used to initiate conversions in low-power trac king mode, adc0 tracks only when cnvstr is low; conversion begins on the rising edge of cnvstr (see figure 7.2 ). tracking can also be disabled (shutdown) w hen the device is in low power standby or sleep modes. low-power track-and-hold mode is also usef ul when amux settings are frequently changed, due to the settling time requirements described in section ?7.2.3. settling time requirements? on page 47 .
write '1' to ad0busy, timer 0, timer 2, timer 1, timer 3 overflow (ad0cm[2:0]=000, 001,010 011, 101) ad0tm=1 track convert low power mode ad0tm=0 track or convert convert track low power or convert sar clocks sar clocks b. adc0 timing for internal trigger source 123456789 cnvstr (ad0cm[2:0]=100) ad0tm=1 a. adc0 timing for external trigger source sar clocks track or convert convert track ad0tm=0 track convert low power mode low power or convert 10 11 12 13 14 123456789 10 11 12 13 14 123456789 10 11 12 13 14 15 16 17 c8051f336/7/8/9 46 rev. 0.2 figure 7.2. 10-bit adc track and conversion example timing
rev. 0.2 47 c8051f336/7/8/9 7.2.3. settling time requirements a minimum tracking time is required before each conversi on to ensure that an accurate conversion is per - formed. this tracking time is determined by any se ries impedance, including the amux0 resistance, the the adc0 sampling capacitance, and the accuracy required for the conversion. note that in low-power tracking mode, three sar clocks are used for tracking at the start of every conversion. for many applica - tions, these three sar clocks will meet t he minimum tracking time requirements. figure 7.3 shows the equivalent adc0 input circuits for both differential and single-ended modes. notice that the equivalent time constant for both input circ uits is the same. the required adc0 settling time for a given settling accuracy (sa) may be approximated by equation 7.1 . when measuring the temperature sensor output or v dd with respect to gnd, r total reduces to r mux . see ta b l e 6.8 for adc0 minimum settling time requirements as well as the mux impedance and sampling capacitor values. t 2 n sa ------ - ?? ?? r total c sample ln = equation 7.1. adc0 settling time requirements where: sa is the settling accuracy, given as a fraction of an lsb (for example, 0.25 to settle within 1/4 lsb) t is the required settling time in seconds r total is the sum of the amux0 resistance and any external source resistance. n is the adc resolution in bits (10). r mux rc input = r mux * c sample r mux c sample c sample mux select mux select differential mode px.x px.x r mux c sample rc input = r mux * c sample mux select single-ended mode px.x figure 7.3. adc0 eq uivalent input circuits
sfr definition 7.1. adc0cf: adc0 configuration bit 7 6 5 4 3 2 1 0 name ad0sc[4:0] ad0ljst type r/w r/w r r reset 1 1 1 1 1 0 0 0 c8051f336/7/8/9 48 rev. 0.2 sfr address = 0xbc bit name function 7:3 ad0sc[4:0] adc0 sar conversion cl ock period bits. sar conversion clock is derived from syste m clock by the following equation, where ad0sc refers to the 5-bit value held in bits ad0sc4 ? 0. sar conversion clock requirements are given in the adc specification table. ad0sc sysclk clk sar ------------ ---------- - 1 ? = 2 ad0ljst adc0 left justify select. 0: data in adc0h:adc0l re gisters are right-justified. 1: data in adc0h:adc0l re gisters are left-justified. 1:0 unused unused. read = 00b; write = don?t care.
sfr definition 7.2. adc0h: adc0 data word msb bit 7 6 5 4 3 2 1 0 name adc0h[7:0] type r/w reset 0 0 0 0 0 0 0 0 rev. 0.2 49 c8051f336/7/8/9 sfr address = 0xbe bit name function 7:0 adc0h[7:0] adc0 data word high-order bits. for ad0ljst = 0: bits 7 ? 2 are the sign extension of bit1. bits 1 ? 0 are the upper 2 bits of the 10-bit adc0 data word. for ad0ljst = 1: bits 7 ? 0 are the most-significant bits of the 10-bit adc0 data word. sfr definition 7.3. adc0l: adc0 data word lsb bit 7 6 5 4 3 2 1 0 name adc0l[7:0] type r/w reset 0 0 0 0 0 0 0 0 sfr address = 0xbd bit name function 7:0 adc0l[7:0] adc0 data word low-order bits. for ad0ljst = 0: bits 7 ? 0 are the lower 8 bits of the 10-bit data word. for ad0ljst = 1: bits 7 ? 6 are the lower 2 bits of the 10-bit data word. bits 5 ? 0 will always read ?0?.
sfr definition 7.4. adc0cn: adc0 control bit 7 6 5 4 3 2 1 0 name ad0en ad0tm ad0int ad0busy ad0wint ad0cm[2:0] type r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 c8051f336/7/8/9 50 rev. 0.2 sfr address = 0xe8; bit-addressable bit name function 7 ad0en adc0 enable bit. 0: adc0 disabled. adc0 is in low-power shutdown. 1: adc0 enabled. adc0 is active and ready for data conversions. 6 ad0tm adc0 track mode bit. 0: normal track mode: when adc0 is ena bled, tracking is continuous unless a con - version is in progress. conversion begins immediately on start-of-conversion event, as defined by ad0cm[2:0]. 1: low-power track mode: for ad0cm[2:0] = 100, adc is tracking when cnvstr is low, and conversion begins immediat ely on rising edge of cnvstr. for all other values of ad0cm[2:0], tracking is initiated on start-of-conversion event, and lasts 3 sar clock cycles. the conversi on immediately follows this tracking phase. 5 ad0int adc0 conversion comple te interrupt flag. 0: adc0 has not completed a data conv ersion since ad0int was last cleared. 1: adc0 has completed a data conversion. 4 ad0busy adc0 busy bit. read: 0: adc0 conversion is not in progress. 1: adc0 conversion is in progress. write: 0: no effect. 1: initiates adc0 conver - sion if ad0cm[2 : 0] = 000b 3 ad0wint adc0 window compare interrupt flag. 0: adc0 window comparison data match ha s not occurred since this flag was last cleared. 1: adc0 window comparison data match has occurred. 2:0 ad0cm[2:0] adc0 start of conversion mode select. 000: adc0 start-of-conversion sour ce is write of ?1? to ad0busy. 001: adc0 start-of-conversion source is overflow of timer 0. 010: adc0 start-of-conversion source is overflow of timer 2. 011: adc0 start-of-conversion source is overflow of timer 1. 100: adc0 start-of-conversion source is rising edge of external cnvstr. 101: adc0 start-of-conversion source is overflow of timer 3. 11x: reserved.
rev. 0.2 51 c8051f336/7/8/9 7.3. programmable window detector the adc programmable window detector continuously compares the adc0 output registers to user-pro - grammed limits, and notifies the system when a desired co ndition is detected. this is especially effective in an interrupt-driven system, saving code space and cpu ba ndwidth while delivering faster system response times. the window detector interrupt flag (ad0wint in register adc0cn) can also be used in polled mode. the adc0 greater-t han (adc0gth, adc0gtl) and less-than (adc0lth, adc0ltl) reg - isters hold the comparison values. the window detector flag can be programmed to indicate when mea - sured data is inside or outside of the user-progr ammed limits, depending on the contents of the adc0 less-than and adc0 greater-than registers. sfr definition 7.5. adc0gth: adc0 greater-than data high byte bit 7 6 5 4 3 2 1 0 name adc0gth[7:0] type r/w reset 1 1 1 1 1 1 1 1 sfr address = 0xc4 bit name function 7:0 adc0gth[7:0] adc0 greater-than data word high-order bits. sfr definition 7.6. adc0gtl: adc0 greater-than data low byte bit 7 6 5 4 3 2 1 0 name adc0gtl[7:0] type r/w reset 1 1 1 1 1 1 1 1 sfr address = 0xc3 bit name function 7:0 adc0gtl[7:0] adc0 greater-than data word low-order bits.
sfr definition 7.7. adc0lth: adc0 less-than data high byte bit 7 6 5 4 3 2 1 0 name adc0lth[7:0] type r/w reset 0 0 0 0 0 0 0 0 c8051f336/7/8/9 52 rev. 0.2 sfr address = 0xc6 bit name function 7:0 adc0lth[7:0] adc0 less-than data word high-order bits. sfr definition 7.8. adc0ltl: adc0 less -than data low byte bit 7 6 5 4 3 2 1 0 name adc0ltl[7:0] type r/w reset 0 0 0 0 0 0 0 0 sfr address = 0xc5 bit name function 7:0 adc0ltl[7:0] adc0 less-than data word low-order bits.
rev. 0.2 53 c8051f336/7/8/9 7.3.1. window detector in single-ended mode figure 7.4 shows two example window comparisons fo r right-justified, single-ended data, with adc0lth:adc0ltl = 0x0080 (128d) and adc0gth:adc0gtl = 0x0040 (64d). in single-ended mode, the input voltage can range from ?0? to vref x (1023/ 1024) with respect to gnd, and is represented by a 10-bit unsigned intege r value. in the left example, an ad0win t interrupt will be gener ated if the adc0 conversion word (adc0h:adc0l) is within the range defined by adc0gth:adc0gtl and adc0lth:adc0ltl (if 0x0040 < adc0h:adc0l < 0x0080). in the right example, and ad0wint interrupt will be generated if the adc0 conversion word is outside of t he range defined by the adc0gt and adc0lt registers (if adc0h:adc0l < 0x0040 or adc0h:adc0l > 0x0080). figure 7.5 shows an exam - ple using left-justified data with the same comparison values. 0x03ff 0x0081 0x0080 0x007f 0x0041 0x0040 0x003f 0x0000 0 input voltage (px.x - gnd) vref x (1023/1024) vref x (128/1024) vref x (64/1024) ad0wint=1 ad0wint not affected ad0wint not affected adc0lth:adc0ltl adc0gth:adc0gtl 0x03ff 0x0081 0x0080 0x007f 0x0041 0x0040 0x003f 0x0000 0 input voltage (px.x - gnd) vref x (1023/1024) vref x (128/1024) vref x (64/1024) ad0wint not affected ad0wint=1 ad0wint=1 adc0h:adc0l adc0h:adc0l adc0gth:adc0gtl adc0lth:adc0ltl 0xffc0 0x2040 0x2000 0x1fc0 0x1040 0x1000 0x0fc0 0x0000 0 input voltage (px.x - gnd) vref x (1023/1024) vref x (128/1024) vref x (64/1024) ad0wint=1 ad0wint not affected ad0wint not affected adc0lth:adc0ltl adc0gth:adc0gtl 0xffc0 0x2040 0x2000 0x1fc0 0x1040 0x1000 0x0fc0 0x0000 0 input voltage (px.x - gnd) vref x (1023/1024) vref x (128/1024) vref x (64/1024) ad0wint not affected ad0wint=1 ad0wint=1 adc0h:adc0l adc0h:adc0l adc0lth:adc0ltl adc0gth:adc0gtl figure 7.4. adc window co mpare example: right-justified single-ended data figure 7.5. adc window co mpare example: left-justified single-ended data
c8051f336/7/8/9 54 rev. 0.2 7.3.2. window detector in differential mode figure 7.6 shows two example window comparisons for right-justified, differential data, with adc0lth:adc0ltl = 0x0040 (+64d) and adc0gth:adc0gth = 0xffff ( ? 1d). in differential mode, the measurable voltage between the input pins is between ?vref and vref x (511/512). output codes are represented as 10-bit 2s complement signed integers. in the left example, an ad0wint interrupt will be generated if the adc0 conversion word (a dc0h:adc0l) is within the range defined by adc0gth:adc0gtl and adc0lth:adc0ltl (if 0xffff (?1d) < adc0h:adc0l < 0x0040 (64d)). in the right example, an ad0wint interrupt will be generated if the adc0 conver sion word is outside of the range defined by the adc0gt and adc0lt registers (if adc0h:adc0l < 0xffff (?1d) or adc0h:adc0l > 0x0040 (+64d)). figure 7.7 shows an example using left-justified data with the same comparison values. 0x01ff 0x0041 0x0040 0x003f 0x0000 0xffff 0xfffe 0x0200 -vref input voltage (px.x - px.x) vref x (511/512) vref x (64/512) vref x (-1/512) 0x01ff 0x0041 0x0040 0x003f 0x0000 0xffff 0xfffe 0x0200 -vref input voltage (px.x - px.x) vref x (511/512) vref x (64/512) vref x (-1/512) ad0wint=1 ad0wint not affected ad0wint not affected adc0lth:adc0ltl adc0gth:adc0gtl ad0wint not affected ad0wint=1 ad0wint=1 adc0h:adc0l adc0h:adc0l adc0gth:adc0gtl adc0lth:adc0ltl 0x7fc0 0x1040 0x1000 0x0fc0 0x0000 0xffc0 0xff80 0x8000 -vref input voltage (px.x - px.y) vref x (511/512) vref x (64/512) vref x (-1/512) 0x7fc0 0x1040 0x1000 0x0fc0 0x0000 0xffc0 0xff80 0x8000 -vref input voltage (px.x - px.x) vref x (511/512) vref x (64/512) vref x (-1/512) ad0wint=1 ad0wint not affected ad0wint not affected adc0lth:adc0ltl adc0gth:adc0gtl ad0wint not affected adc0gth:adc0gtl ad0wint=1 ad0wint=1 adc0h:adc0l adc0h:adc0l adc0lth:adc0ltl figure 7.6. ad c window compare example: righ t-justified differential data figure 7.7. adc window compare exampl e: left-justified differential data
rev. 0.2 55 c8051f336/7/8/9 7.4. adc0 analog multip lexer (c8051f336/8 only) adc0 on the c8051f336/8 has two analog mult iplexers, referred to collectively as amux0. amux0 selects the positive and negative inputs to th e adc. any of the following may be selected as the positive input: port i/o pins, the on-chip temperature sensor, or the positive power supply (v dd ). any of the following may be selected as the negative input: port i/o pins, v ref , or gnd. when gnd is selected as the negative input, adc0 operate s in single-ended mode ; all other times, adc0 operates in differ - ential mode. the adc0 input channels are selected in t he amx0p and amx0n registers as described in sfr definition 7.9 and sfr definition 7.10 . adc0 amux temp sensor amux vdd gnd p0.0 p2.3* amx0p amx0p4 amx0p3 amx0p2 amx0p1 amx0p0 amx0n amx0n4 amx0n3 amx0n2 amx0n1 amx0n0 ain+ ain- vref p0.0 p2.3* *p2.0-p2.3 only available as inputs on qfn24 packaging figure 7.8. adc0 multip lexer block diagram important note about adc0 input configuration: port pins selected as adc0 inputs should be config - ured as analog inputs, and should be skipped by the digital crossbar. to configure a port pin for analog input, set to ?0? the corresponding bit in register pnmdin. to force the cros sbar to skip a port pin, set to ?1? the corresponding bit in register pnskip. see section ?20. port input/output? on page 126 for more port i/o configuration details.
sfr definition 7.9. amx0p: amux0 positive channel select bit 7 6 5 4 3 2 1 0 name amx0p[4:0] type r r r r/w reset 0 0 0 1 1 1 1 1 c8051f336/7/8/9 56 rev. 0.2 sfr address = 0xbb bit name function 7:5 unused unused. read = 000b; write = don?t care. 4:0 amx0p[4:0] amux0 positive input selection. 00000: p0.0 00001: p0.1 00010: p0.2 00011: p0.3 00100: p0.4 00101: p0.5 00110: p0.6 00111: p0.7 01000: p1.0 01001: p1.1 01010: p1.2 01011: p1.3 01100: p1.4 01101: p1.5 01110: p1.6 01111: p1.7 10000: temp sensor 10001: v dd 10010: p2.0 (c8051f338/9 only) 10011: p2.1 (c8051f338/9 only) 10100: p2.2 (c8051f338/9 only) 10101: p2.3 (c8051f338/9 only) 10110 ? 11111: no input selected
sfr definition 7.10. amx0n: amux0 negative channel select bit 7 6 5 4 3 2 1 0 name amx0n[4:0] type r r r r/w reset 0 0 0 1 1 1 1 1 rev. 0.2 57 c8051f336/7/8/9 sfr address = 0xba bit name function 7:5 unused unused. read = 000b; write = don?t care. 4:0 amx0n[4:0] amux0 negative input selection. 00000: p0.0 00001: p0.1 00010: p0.2 00011: p0.3 00100: p0.4 00101: p0.5 00110: p0.6 00111: p0.7 01000: p1.0 01001: p1.1 01010: p1.2 01011: p1.3 01100: p1.4 01101: p1.5 01110: p1.6 01111: p1.7 10000: v ref 10001: gnd (adc in single-ended mode) 10010: p2.0 (c8051f338/9 only) 10011: p2.1 (c8051f338/9 only) 10100: p2.2 (c8051f338/9 only) 10101: p2.3 (c8051f338/9 only) 10110 ? 11111: no input selected
c8051f336/7/8/9 58 rev. 0.2 8. temperature sensor (c8051f336/8 only) an on-chip temperature sensor is included on the c8051f336/8 which can be directly accessed via the adc multiplexer in single -ended configuration. to use the adc to measure the temperature sensor, the positive adc mux channel should be configured to connect to the temperature sensor and the negative adc mux channel should be configured to connect to gnd. the temperature sensor transfer function is shown in figure 8.1 . the output voltage (v temp ) is the positive adc input wh en the adc multiplexer is set correctly. the tempe bit in register ref0cn enables /disables the temperature sensor, as described in sfr definition 10.1 . while disabled, the temperature sensor defaults to a high impedance state and any adc measurements perf ormed on the sensor will result in meaningless data. refer to ta b l e 6.9 for the slope and offset parameters of the temperature sensor. temperature voltage v temp = ( slope x temp c ) + offset offset (v at 0 celsius) slope (v / deg c) temp c = (v temp - offset ) / slope figure 8.1. temperature sensor transfer function
rev. 0.2 59 c8051f336/7/8/9 9. 10-bit current mode dac (ida0, c8051f336/8 only) the c8051f336/8 device includes a 10-bit current -mode digital-to-analog co nverter (idac). the maxi - mum current output of the idac can be adjust ed for three different current settings; 0.5 ma, 1 ma, and 2 ma. the idac is enabled or disabled with the ida0en bit in the ida0 control register (see sfr defini - tion 9.1 ). when ida0en is set to ?0?, the idac port pi n (p0.1) behaves as a normal gpio pin. when ida0en is set to ?1?, the digital output drivers and weak pullup for the idac pin are automatically disabled, and the pin is connected to the idac output. an intern al bandgap bias generator is used to generate a ref - erence current for the idac whenever it is enabled. when using the idac, bit 1 in the p0skip register should be set to ?1?, to force the crossbar to skip the idac pin. 9.1. ida0 output scheduling ida0 features a flexible output update mechanism which allows for seamless full-scale changes and sup - ports jitter-free updates for wavefo rm generation. three update modes are provided, allowing idac output updates on a write to ida0h, on a time r overflow, or on an external pin edge. 9.1.1. update output on-demand in its default mode (ida0cn.[6:4] = ?111?) the ida0 output is updated ?on-demand? on a write to the high- byte of the ida0 data register (ida0h). it is important to note that writes to ida0l are held in this mode, and have no effect on the ida0 output until a write to ida0h takes place. if writing a full 10-b it word to the idac data registers, the 10-bit data word is written to the low byte (ida0l) and high byte (ida0h) data reg - isters. data is latched into ida0 after a write to the ida0h register, so the write sequence should be ida0l followed by ida0h if the full 10-bit resolution is required. the idac can be used in 8-bit mode by initializing ida0l to the desired va lue (typically 0x00), and writ ing data to only ida0h (see section 9.2 for information on the format of the 10-bit idac data word within the 16-bit sfr space). ida0 10 ida0 ida0cn ida0en ida0cm2 ida0cm1 ida0cm0 ida0omd1 ida0omd0 ida0h ida0l latch 8 2 ida0h timer 0 timer 1 timer 2 timer 3 cnvstr figure 9.1. ida0 fun ctional block diagram
c8051f336/7/8/9 60 rev. 0.2 9.1.2. update output based on timer overflow similar to the adc operation, in which an adc conv ersion can be initiated by a timer overflow indepen - dently of the processor, the idac outputs can use a timer overflow to schedule an output update event. this feature is useful in systems where the idac is used to generate a waveform of a defined sampling rate by eliminating the effects of variable interrupt la tency and instruction execution on the timing of the idac output. when the ida0cm bits (ida0cn.[6:4]) are se t to ?000?, ?001?, ?010? or ?011?, writes to both idac data registers (ida0l and ida0h) are held until an associated timer overflow event (timer 0, timer 1, timer 2 or timer 3, respectively) occurs, at which time the ida0h:ida0l contents are copied to the idac input latches, a llowing the idac output to change to the new value. 9.1.3. update output based on cnvstr edge the idac output can also be configured to update on a rising edge, falling edge, or both edges of the external cnvstr signal. when the ida0cm bits (ida0cn.[6:4]) are set to ?100?, ?101?, or ?110?, writes to both idac data registers (ida0l and ida0h) are held until an edge occurs on the cnvstr input pin. the particular setting of the ida0cm bi ts determines whether idac outputs are updated on ri sing, falling, or both edges of cnvstr. when a corresponding edge oc curs, the ida0h:ida0l contents are copied to the idac input latches, allowing the idac output to change to the new value. 9.2. idac output mapping the idac data registers (ida0h and ida0l) are left-j ustified, meaning that the eight msbs of the idac output word are mapped to bits 7 ? 0 of the ida0h register, and the two lsbs of the idac output word are mapped to bits 7 and 6 of the ida0l register. the data word mapping for the idac is shown in figure 9.2 . ida0h ida0l ida09ida08ida07ida06ida05ida04ida03ida02ida01ida00 input data word (ida09?ida00) output current ida0omd[1:0] = ?1x? output current ida0omd[1:0] = ?01? output current ida0omd[1:0] = ?00? 0x000 0 ma 0 ma 0 ma 0x001 1/1024 x 2 ma 1/1024 x 1 ma 1/1024 x 0.5 ma 0x200 512/1024 x 2 ma 512/1024 x 1 ma 512/1024 x 0.5 ma 0x3ff 1023/1024 x 2 ma 1023/1024 x 1 ma 1023/1024 x 0.5 ma figure 9.2. ida0 data word mapping the full-scale output current of the idac is selected using the ida0omd bits (ida0cn[1:0]). by default, the idac is set to a full-scale output current of 2 ma. the ida0omd bits can also be configured to provide full-scale output currents of 1 ma or 0.5 ma, as shown in sfr definition 9.1 .
sfr definition 9.1. ida0cn: ida0 control bit 7 6 5 4 3 2 1 0 name ida0en ida0cm[2:0] ida0omd[1:0] type r/w r/w r r r/w reset 0 1 1 1 0 0 1 0 rev. 0.2 61 c8051f336/7/8/9 sfr address = 0xb9 bit name function 7 ida0en ida0 enable. 0: ida0 disabled. 1: ida0 enabled. 6:4 ida0cm[2:0] ida0 update source select bits. 000: dac output updates on timer 0 overflow. 001: dac output updates on timer 1 overflow. 010: dac output updates on timer 2 overflow. 011: dac output updates on timer 3 overflow. 100: dac output updates on rising edge of cnvstr. 101: dac output updates on falling edge of cnvstr. 110: dac output updates on any edge of cnvstr. 111: dac output updates on write to ida0h. 3:2 unused unused. read = 00b. write = don?t care. 1:0 ida0omd[1:0] ida0 output mode select bits. 00: 0.5 ma full-scale output current. 01: 1.0 ma full-scale output current. 1x: 2.0 ma full-scale output current.
sfr definition 9.2. ida0h: ida0 data word msb bit 7 6 5 4 3 2 1 0 name ida0[9:2] type r/w reset 0 0 0 0 0 0 0 0 c8051f336/7/8/9 62 rev. 0.2 sfr address = 0x97 bit name function 7:0 ida0[9:2] ida0 data word high-order bits. upper 8 bits of the 10-bit ida0 data word. sfr definition 9.3. ida0l: ida0 data word lsb bit 7 6 5 4 3 2 1 0 name ida0[1:0] type r/w r r r r r r reset 0 0 0 0 0 0 0 0 sfr address = 0x96 bit name function 7:6 ida0[1:0] ida0 data word low-order bits. lower 2 bits of the 10-bit ida0 data word. 5:0 unused unused. read = 000000b. write = don?t care.
rev. 0.2 63 c8051f336/7/8/9 10. voltage reference (c8051f336/8 only) the voltage reference multiplexer for the adc is configurable to use an externally connected voltage refer - ence, the on-chip reference voltage genera tor routed to the vref pin, or the v dd power supply voltage (see figure 10.1 ). the refsl bit in the reference control register (ref0cn, sfr definition 10.1 ) selects the reference source for the adc. for an external sour ce or the on-chip reference, refsl should be set to ?0? to select the vref pin. to use v dd as the reference source, refsl should be set to ?1?. the biase bit enables the inte rnal voltage bias ge nerator, which is used by ma ny of the analo g peripherals on the device. this bias is automatically enabled when any peripheral which requires it is enabled, and it does not need to be enabled manually. the bias generator may be enabled manually by writing a ?1? to the biase bit in register ref0cn. the el ectrical specifications for the volt age reference circuit are given in ta b l e 6.10 . the on-chip voltage reference circuit consists of a 1.2 v, temperature stable bandgap voltage reference generator and a gain-of-two output buffer amplifier. the on-chip voltage reference can be driven on the vref pin by setting the refbe bit in register ref0cn to a ?1?. the maximum load seen by the vref pin must be less than 200 a to gnd. bypass capacitors of 0.1 f and 4.7 f are recommended from the vref pin to gnd. if the on-chip reference is not used , the refbe bit should be cleared to ?0?. electrical specifications for the on-chip voltage reference are given in ta b l e 6.10 . important note about the vref pin: when using either an external vo ltage reference or the on-chip ref - erence circuitry, the vref pin should be configured as an analog pin and skipped by the digital crossbar. refer to section ?20. port input/output? on page 126 for the location of the vref pin, as well as details of how to configure the pin in analog mode and to be skipped by the crossbar. vref (to adc) to analog mux vdd vref r1 vdd external voltage reference circuit gnd temp sensor en bias generator to adc, idac, internal oscillators en iosce n 0 1 ref0cn refsl tempe biase refbe refbe internal reference en recommended bypass capacitors + 4.7 f0.1 f figure 10.1. voltage reference functional block diagram
sfr definition 10.1. ref0cn: reference control bit 7 6 5 4 3 2 1 0 name refsl tempe biase refbe type r r r r r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 c8051f336/7/8/9 64 rev. 0.2 sfr address = 0xd1 bit name function 7:4 unused unused. read = 0000b; write = don?t care. 3 refsl voltage reference select. this bit selects the adcs voltage reference. 0: v ref pin used as voltage reference. 1: v dd used as voltage reference. 2 tempe temperature sensor enable bit. 0: internal temperature sensor off. 1: internal temperature sensor on. 1 biase internal analog bias generator enable bit. 0: internal bias generator off. 1: internal bias generator on. 0 refbe on-chip reference buffer enable bit. 0: on-chip reference buffer off. 1: on-chip reference buffer on. internal voltage reference driven on the v ref pin.
rev. 0.2 65 c8051f336/7/8/9 11. comparator0 c8051f336/7/8/9 devices include an on-chip programmable voltage comparator, comparator0, shown in figure 11.1 . the comparator offers programmable response time a nd hysteresis, an analog in put multiplexer, and two outputs that are optionally avail able at the port pins: a synchronous ?latched? output (cp0), or an asyn - chronous ?raw? output (cp0a). the asynchronous cp0a signal is available even when the system clock is not active. this allows the comparator to operate and generate an output with the device in stop mode. when assigned to a port pin, the comparator outpu t may be configured as open drain or push-pull (see section ?20.4. port i/o initialization? on page 133 ). comparator0 may also be used as a reset source (see section ?18.5. comparator0 reset? on page 114 ). the comparator0 inputs are selected by the comparator input multiplexer, as detailed in section ?11.1. comparator multip lexer? on page 70 . vdd reset decision tree + - crossbar q q set clr d q q set clr d (synchronizer) gnd cp0 + cp0 - cpt0md cp0rie cp0fie cp0md1 cp0md0 cp0 cp0a cp0 interrupt 0 1 0 1 cp0rif cp0fif 0 1 cp0en 0 1 ea comparator input mux cpt0cn cp0en cp0out cp0rif cp0fif cp0hyp1 cp0hyp0 cp0hyn1 cp0hyn0 figure 11.1. comparator0 functional block diagram
c8051f336/7/8/9 66 rev. 0.2 the comparator output can be polled in software, used as an interrupt source, and/or routed to a port pin. when routed to a port pin, the comp arator output is available asynch ronous or synchronous to the system clock; the asynchronous output is available even in stop mode (with no system clock active). when dis - abled, the comparator output (if assigned to a port i/o pin via the crossbar) defaults to the logic low state, and the power supply to the co mparator is turned off. see section ?20.3. priority crossbar decoder? on page 131 for details on configuring comparator outputs via the digital crossbar. comparator inputs can be externally driven from ?0.25 v to (v dd ) + 0.25 v without damage or upset. the complete comparator elec - trical specifications are given in ta b l e 6.12 . the comparator response time may be configured in software via the cpt0md register (see sfr defini - tion 11.2 ). selecting a longer response time reduces the comparator supply current. positive hysteresis voltage (programmed with cp0hyp bits) negative hysteresis voltage (programmed by cp0hyn bits) vin- vin+ inputs circuit configuration + _ cp0+ cp0- cp0 vin+ vin- out v oh positive hysteresis disabled maximum positive hysteresis negative hysteresis disabled maximum negative hysteresis output v ol figure 11.2. compar ator hysteresis plot the comparator hysteresis is software-programmabl e via its comparator control register cpt0cn. the user can program both the amount of hysteresis voltage (referred to the input voltage) and the positive and negative-going symmetry of this hyst eresis around the threshold voltage. the comparator hysteresis is programmed using bits3 ? 0 in the comparator co ntrol register cpt0cn (shown in sfr definition 11.1 ). the amount of negative hysteresis voltage is dete rmined by the settings of the cp0hyn bits. as shown in figure 11.2 , settings of 20, 10 or 5 mv of negative hysteresis can be pro - grammed, or negative hysteresis can be disabled. in a similar way, the amount of positive hysteresis is determined by the setting the cp0hyp bits. comparator interrupts can be genera ted on both rising-e dge and falling-edge output transitions. (for inter - rupt enable and priority control, see section ?15.1. mcu interrupt sources and vectors? on page 90 ). the cp0fif flag is set to logic 1 upon a comparator falling-edge occurren ce, and the cp0rif flag is set to
rev. 0.2 67 c8051f336/7/8/9 logic 1 upon the comparator rising-edge occurrence. once set, these bits remain set until cleared by soft - ware. the comparator rising-edge interrupt mask is enabled by setting cp0rie to a logic 1. the comparator0 falling-edg e interrupt mask is enabled by setting cp0fie to a logic 1. the output state of the comparator can be obtained at any time by reading the cp0out bit. the compar - ator is enabled by setting the cp0en bit to logic 1, and is disabled by clearing this bit to logic 0. note that false rising ed ges and falling edges can be detected when the comparator is fi rst powered on or if changes are made to the hy steresis or response time control bits. therefore, it is recommended that the rising-edge and falling-edge flags be explicitly cleared to logic 0 a short time after the comparator is enabled or its mode bits have been changed.
sfr definition 11.1. cpt0cn: comparator0 control bit 7 6 5 4 3 2 1 0 name cp0en cp0out cp0rif cp0fif cp0hyp[1:0] cp0hyn[1:0] type r/w r r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 c8051f336/7/8/9 68 rev. 0.2 sfr address = 0x9b bit name function 7 cp0en comparator0 enable bit. 0: comparator0 disabled. 1: comparator0 enabled. 6 cp0out comparator0 output state flag. 0: voltage on cp0+ < cp0 ? . 1: voltage on cp0+ > cp0 ? . 5 cp0rif comparator0 rising-edge flag. must be cleared by software. 0: no comparator0 rising edge has occurred since this flag was last cleared. 1: comparator0 rising edge has occurred. 4 cp0fif comparator0 falling-edge flag. must be cleared by software. 0: no comparator0 falling-edge has occu rred since this flag was last cleared. 1: comparator0 falling- edge has occurred. 3:2 cp0hyp[1:0] comparator0 positive hysteresis control bits. 00: positive hysteresis disabled. 01: positive hysteresis = 5 mv. 10: positive hysteresis = 10 mv. 11: positive hysteresis = 20 mv. 1:0 cp0hyn[1:0] comparator0 negative hysteresis control bits. 00: negative hysteresis disabled. 01: negative hysteresis = 5 mv. 10: negative hysteresis = 10 mv. 11: negative hysteresis = 20 mv.
sfr definition 11.2. cpt0md: comparator0 mode selection bit 7 6 5 4 3 2 1 0 name cp0rie cp0fie cp0md[1:0] type r r r/w r/w r r r/w reset 0 0 0 0 0 0 1 0 rev. 0.2 69 c8051f336/7/8/9 sfr address = 0x9d bit name function 7:6 unused unused. read = 00b, write = don?t care. 5 cp0rie comparator0 rising-edge interrupt enable. 0: comparator0 rising-edge interrupt disabled. 1: comparator0 rising-edge interrupt enabled. 4 cp0fie comparator0 falling-edge interrupt enable. 0: comparator0 falling-edge inte rrupt disabled. 1: comparator0 falling-edge inte rrupt enabled. 3:2 unused unused. read = 00b, write = don?t care. 1:0 cp0md[1:0] comparator0 mode select. these bits affect the response time and power consumption for comparator0. 00: mode 0 (fastest response time, highest power consumption) 01: mode 1 10: mode 2 11: mode 3 (slowest response time, lowest power consumption)
c8051f336/7/8/9 70 rev. 0.2 11.1. comparator multiplexer c8051f336/7/8/9 devices include an analog input multip lexer to connect port i/o pins to the comparator inputs. the comparator0 inputs are selected in the cpt0mx register ( sfr definition 11.3 ). the cmx0p1 ? cmx0p0 bits select the comparator0 positive input; the cmx0n1 ? cmx0n0 bits select the comparator0 negative input. important note about comparator inputs: the port pins selected as comparator inputs should be configured as analog inputs in their associat ed port configuration register, and configured to be skipped by the crossbar (for details on port configuration, see section ?20.6. special function registers for accessing and configuring port i/o? on page 138 ). + - cp0 + p0.0 cp0 - cpt0mx cmx0n3 cmx0n2 cmx0n1 cmx0n0 cmx0p3 cmx0p2 cmx0p1 cmx0p0 p0.2 p0.4 p0.6 p1.0 p1.2 p1.4 p1.6 p2.0* p2.2* p0.1 p0.3 p0.5 p0.7 p1.1 p1.3 p1.5 p1.7 p2.1* p2.3* gnd vdd *p2.0-p2.3 only available as inputs on qfn24 packaging figure 11.3. comparator input multiplexer block diagram
sfr definition 11.3. cpt0mx: comparator0 mux selection bit 7 6 5 4 3 2 1 0 name cmx0n[3:0] cmx0p[3:0] type r/w r/w reset 1 1 1 1 1 1 1 1 rev. 0.2 71 c8051f336/7/8/9 sfr address = 0x9f bit name function 7:4 cmx0n[3:0] comparator0 negative input mux selection. 0000: p0.1 0001: p0.3 0010: p0.5 0011: p0.7 0100: p1.1 0101: p1.3 0110: p1.5 0111: p1.7 1000: p2.1 (c8051f338/9 only) 1001: p2.3 (c8051f338/9 only) 1010-1111: none 3:0 cmx0p[3:0] comparator0 positive input mux selection. 0000: p0.0 0001: p0.2 0010: p0.4 0011: p0.6 0100: p1.0 0101: p1.2 0110: p1.4 0111: p1.6 1000: p2.0 (c8051f338/9 only) 1001: p2.2 (c8051f338/9 only) 1010-1111: none
c8051f336/7/8/9 72 rev. 0.2 12. cip-51 microcontroller the mcu system controller core is the cip-51 microcon troller. the cip-51 is fully compatible with the mcs-51? instruction set; standard 803x/805x assemble rs and compilers can be used to develop soft - ware. the mcu family has a superset of all the peri pherals included with a standard 8051. the cip-51 also includes on-chip debug hardware (see description in section 26 ), and interfaces directly with the ana - log and digital subsystems providing a complete data ac quisition or control-system solution in a single inte - grated circuit. the cip-51 microcontroller core implements the standard 8051 organization and peripherals as well as additional custom peripherals and f unctions to extend its capability (see figure 12.1 for a block diagram). the cip-51 includes the following features: - fully compatible wit h mcs-51 instruction set - 25 mips peak throughput with 25 mhz clock - 0 to 25 mhz clock frequency - extended interrupt handler - reset input - power management modes - on-chip debug logic - program and data memory security performance the cip-51 employs a pipelined architecture that grea tly increases its instruction throughput over the stan - dard 8051 architecture. in a standar d 8051, all instructions except for mul and div take 12 or 24 system clock cycles to execute, and usually have a maximum system clock of 12 mhz. by contrast, the cip-51 core executes 70% of its instructions in one or tw o system clock cycles, with no instructions taking more than eight system clock cycles. data bus tmp1 tmp2 prgm. address reg. pc incrementer alu psw data bus data bus memory interface mem_address d8 pipeline buffer data pointer interrupt interface system_irqs emulation_irq mem_control control logic a16 program counter (pc) stop clock reset idle power control register data bus sfr bus interface sfr_address sfr_control sfr_write_data sfr_read_data d8 d8 b register d8 d8 accumulator d8 d8 d8 d8 d8 d8 d8 d8 mem_write_data mem_read_data d8 sram address register sram d8 stack pointer d8 figure 12.1. cip-51 block diagram
rev. 0.2 73 c8051f336/7/8/9 with the cip-51's maximum system clock at 25 mhz, it has a peak throughput of 25 mips. the cip-51 has a total of 109 instructions. the table below shows the to tal number of instructions that require each execu - tion time. clocks to execute 1 2 2/3 3 3/4 4 4/5 5 8 number of instructions 26 50 5 14 7 3 1 2 1 programming and debugging support in-system programming of the flash program memory and communication with on-chip debug support logic is accomplished via the silicon l abs 2-wire development interface (c2). the on-chip debug support logic facilitates full speed in-circuit debugging, a llowing the setting of hardware breakpoints, starting, stopping and single stepping th rough program execution (including interrupt service routines), examination of the program's call stack, a nd reading/writing the conten ts of registers and mem - ory. this method of on-chip debugging is completely non-intrusive, requiring no ram, stack, timers, or other on-chip resources. c2 details can be found in section ?26. c2 interface? on page 229 . the cip-51 is support ed by development tools from silicon labs and third party vendors. silicon labs pro - vides an integrated development environment (ide) in cluding editor, debugger and programmer. the ide's debugger and programmer interface to the cip-51 via th e c2 interface to provide fast and efficient in-sys - tem device programming and debugging. third party macro assemblers and c compilers are also avail - able. 12.1. instruction set the instruction set of the cip-51 system controller is fully compatible with the standard mcs-51? instruc - tion set. standard 8051 development tools can be used to develop software for the cip-51. all cip-51 instructions are the binary and fu nctional equivalent of their mcs-51? counterparts, including opcodes, addressing modes and effect on psw flags. however, in struction timing is different than that of the stan - dard 8051. 12.1.1. instruction and cpu timing in many 8051 implementations, a distinction is ma de between machine cycles and clock cycles, with machine cycles varying from 2 to 12 clock cycles in length. however, the cip-51 implementation is based solely on clock cycle timing. all instructio n timings are specified in terms of clock cycles. due to the pipelined architecture of the cip-51, most instructions execute in the same number of clock cycles as there are program bytes in the instruction. conditional branch instruct ions take one less clock cycle to complete when the branch is not take n as opposed to when the branch is taken. ta b l e 12.1 is the cip-51 instruction set summary, which includes the mnemonic, number of bytes, and number of clock cycles for each instruction.
c8051f336/7/8/9 74 rev. 0.2 table 12.1. cip-51 instruction set summary mnemonic description bytes clock cycles arithmetic operations add a, rn add register to a 1 1 add a, direct add direct byte to a 2 2 add a, @ri add indirect ram to a 1 2 add a, #data add immediate to a 2 2 addc a, rn add register to a with carry 1 1 addc a, direct add direct byte to a with carry 2 2 addc a, @ri add indirect ram to a with carry 1 2 addc a, #data add immediate to a with carry 2 2 subb a, rn subtract register from a with borrow 1 1 subb a, direct subtract direct byte from a with borrow 2 2 subb a, @ri subtract indirect ram from a with borrow 1 2 subb a, #data subtract immediate from a with borrow 2 2 inc a increment a 1 1 inc rn increment register 1 1 inc direct increment direct byte 2 2 inc @ri increment indirect ram 1 2 dec a decrement a 1 1 dec rn decrement register 1 1 dec direct decrement direct byte 2 2 dec @ri decrement indirect ram 1 2 inc dptr increment data pointer 1 1 mul ab multiply a and b 1 4 div ab divide a by b 1 8 da a decimal adjust a 1 1 logical operations anl a, rn and register to a 1 1 anl a, direct and direct byte to a 2 2 anl a, @ri and indirect ram to a 1 2 anl a, #data and immediate to a 2 2 anl direct, a and a to direct byte 2 2 anl direct, #data and immediate to direct byte 3 3 orl a, rn or register to a 1 1 orl a, direct or direct byte to a 2 2 orl a, @ri or indirect ram to a 1 2 orl a, #data or immediate to a 2 2 orl direct, a or a to direct byte 2 2 orl direct, #data or immediate to direct byte 3 3 xrl a, rn exclusive-or register to a 1 1 xrl a, direct exclusive-or direct byte to a 2 2 xrl a, @ri exclusive-or indirect ram to a 1 2 xrl a, #data exclusive-or immediate to a 2 2 xrl direct, a exclusive-or a to direct byte 2 2 xrl direct, #data exclusive-or immediate to direct byte 3 3
rev. 0.2 75 c8051f336/7/8/9 clr a clear a 1 1 cpl a complement a 1 1 rl a rotate a left 1 1 rlc a rotate a left through carry 1 1 rr a rotate a right 1 1 rrc a rotate a right through carry 1 1 swap a swap nibbles of a 1 1 data transfer mov a, rn move register to a 1 1 mov a, direct move direct byte to a 2 2 mov a, @ri move indirect ram to a 1 2 mov a, #data move immediate to a 2 2 mov rn, a move a to register 1 1 mov rn, direct move direct byte to register 2 2 mov rn, #data move immediate to register 2 2 mov direct, a move a to direct byte 2 2 mov direct, rn move register to direct byte 2 2 mov direct, direct move direct byte to direct byte 3 3 mov direct, @ri move indirect ram to direct byte 2 2 mov direct, #data move immediate to direct byte 3 3 mov @ri, a move a to indirect ram 1 2 mov @ri, direct move direct byte to indirect ram 2 2 mov @ri, #data move immediate to indirect ram 2 2 mov dptr, #data16 load dptr with 16-bit constant 3 3 movc a, @a+dptr move code byte relative dptr to a 1 3 movc a, @a+pc move code byte relative pc to a 1 3 movx a, @ri move external data (8-bit address) to a 1 3 movx @ri, a move a to external data (8-bit address) 1 3 movx a, @dptr move external data (16-bit address) to a 1 3 movx @dptr, a move a to external data (16-bit address) 1 3 push direct push direct byte onto stack 2 2 pop direct pop direct byte from stack 2 2 xch a, rn exchange register with a 1 1 xch a, direct exchange direct byte with a 2 2 xch a, @ri exchange indirect ram with a 1 2 xchd a, @ri exchange low nibble of indirect ram with a 1 2 boolean manipulation clr c clear carry 1 1 clr bit clear direct bit 2 2 setb c set carry 1 1 setb bit set direct bit 2 2 cpl c complement carry 1 1 cpl bit complement direct bit 2 2 anl c, bit and direct bit to carry 2 2 table 12.1. cip-51 instructi on set summary (continued) mnemonic description bytes clock cycles
c8051f336/7/8/9 76 rev. 0.2 anl c, /bit and complement of direct bit to carry 2 2 orl c, bit or direct bit to carry 2 2 orl c, /bit or complement of direct bit to carry 2 2 mov c, bit move direct bit to carry 2 2 mov bit, c move carry to direct bit 2 2 jc rel jump if carry is set 2 2/3 jnc rel jump if carry is not set 2 2/3 jb bit, rel jump if direct bit is set 3 3/4 jnb bit, rel jump if direct bit is not set 3 3/4 jbc bit, rel jump if direct bit is set and clear bit 3 3/4 program branching acall addr11 absolute subroutine call 2 3 lcall addr16 long subroutine call 3 4 ret return from subroutine 1 5 reti return from interrupt 1 5 ajmp addr11 absolute jump 2 3 ljmp addr16 long jump 3 4 sjmp rel short jump (relative address) 2 3 jmp @a+dptr jump indirect relative to dptr 1 3 jz rel jump if a equals zero 2 2/3 jnz rel jump if a does not equal zero 2 2/3 cjne a, direct, rel compare direct byte to a and jump if not equal 3 3/4 cjne a, #data, rel compare immediate to a and jump if not equal 3 3/4 cjne rn, #data, rel compare immediate to register and jump if not equal 3 3/4 cjne @ri, #data, rel compare immediate to indirect and jump if not equal 3 4/5 djnz rn, rel decrement register and jump if not zero 2 2/3 djnz direct, rel decrement direct byte and jump if not zero 3 3/4 nop no operation 1 1 table 12.1. cip-51 instructi on set summary (continued) mnemonic description bytes clock cycles
notes on registers, operands and addressing modes: rn - register r0?r7 of the curr ently selected register bank. @ri - data ram location addressed indirectly through r0 or r1. rel - 8-bit, signed (two?s complement) offset relative to the first byte of the following instruction. used by sjmp and all conditional jumps. direct - 8-bit internal data location?s address. this could be a direct-access data ram location (0x00? 0x7f) or an sfr (0x80?0xff). #data - 8-bit constant #data16 - 16-bit constant bit - direct-accessed bit in data ram or sfr addr11 - 11-bit destination address used by acall and ajmp. the destination mu st be within the same 2 kb page of program memory as the first byte of the following instruction. addr16 - 16-bit destination address used by lcall a nd ljmp. the destination may be anywhere within the 8 kb program memory space. there is one unused opcode (0xa5) that performs the same function as nop. all mnemonics copyrighted ? intel corporation 1980. rev. 0.2 77 c8051f336/7/8/9
c8051f336/7/8/9 78 rev. 0.2 12.2. cip-51 regist er descriptions following are descriptions of sfrs related to the operati on of the cip-51 system controller. reserved bits should not be set to logic 1. future product versions may use these bits to implement new features in which case the reset valu e of the bit will be logic 0, selecting the feature's default state. detailed descrip - tions of the remaining sfrs are included in the sect ions of the datasheet asso ciated with their correspond - ing system function. sfr definition 12.1. dpl: data pointer low byte bit 7 6 5 4 3 2 1 0 name dpl[7:0] type r/w reset 0 0 0 0 0 0 0 0 sfr address = 0x82 bit name function 7:0 dpl[7:0] data pointer low. the dpl register is the low byte of the 16 -bit dptr. dptr is used to access indi - rectly addressed flash memory or xram. sfr definition 12.2. dph: data pointer high byte bit 7 6 5 4 3 2 1 0 name dph[7:0] type r/w reset 0 0 0 0 0 0 0 0 sfr address = 0x83 bit name function 7:0 dph[7:0] data pointer high. the dph register is the high byte of the 16-bit dptr. dptr is used to access indi - rectly addressed flash memory or xram.
sfr definition 12.3. sp: stack pointer bit 7 6 5 4 3 2 1 0 name sp[7:0] type r/w reset 0 0 0 0 0 1 1 1 rev. 0.2 79 c8051f336/7/8/9 sfr address = 0x81 bit name function 7:0 sp[7:0] stack pointer. the stack pointer holds the location of the to p of the stack. the stack pointer is incre - mented before every push operation. the sp register defaults to 0x07 after reset. sfr definition 12.4. acc: accumulator bit 7 6 5 4 3 2 1 0 name acc[7:0] type r/w reset 0 0 0 0 0 0 0 0 sfr address = 0xe0; bit-addressable bit name function 7:0 acc[7:0] accumulator. this register is the accumulator for arithmetic operations. sfr definition 12.5. b: b register bit 7 6 5 4 3 2 1 0 name b[7:0] type r/w reset 0 0 0 0 0 0 0 0 sfr address = 0xf0; bit-addressable bit name function 7:0 b[7:0] b register. this register serves as a second accumu lator for certain arithmetic operations.
sfr definition 12.6. psw: program status word bit 7 6 5 4 3 2 1 0 name cy ac f0 rs[1:0] ov f1 parity type r/w r/w r/w r/w r/w r/w r reset 0 0 0 0 0 0 0 0 c8051f336/7/8/9 80 rev. 0.2 sfr address = 0xd0; bit-addressable bit name function 7 cy carry flag. this bit is set when the last arithmetic oper ation resulted in a carry (addition) or a bor - row (subtraction). it is cleared to logi c 0 by all other arithmetic operations. 6 ac auxiliary carry flag. this bit is set when the last arithmetic operat ion resulted in a carry into (addition) or a borrow from (subtraction) the high order nibble. it is cleared to logic 0 by all other arith - metic operations. 5 f0 user flag 0. this is a bit-addressable, general purp ose flag for use under software control. 4:3 rs[1:0] register bank select. these bits select which register bank is used during register accesses. 00: bank 0, addresses 0x00-0x07 01: bank 1, addresses 0x08-0x0f 10: bank 2, addresses 0x10-0x17 11: bank 3, addresses 0x18-0x1f 2 ov overflow flag. this bit is set to 1 under the following circumstances: ? an add, addc, or subb instruction causes a sign-change overflow. ? a mul instruction results in an overflow (result is greater than 255). ? a div instruction causes a divide-by-zero condition. the ov bit is cleared to 0 by the add, a ddc, subb, mul, and div instructions in all other cases. 1 f1 user flag 1. this is a bit-addressable, general purp ose flag for use under software control. 0 parity parity flag. this bit is set to logic 1 if the sum of the ei ght bits in the accumulator is odd and cleared if the sum is even.
rev. 0.2 81 c8051f336/7/8/9 13. memory organization the memory organization of the cip-51 system controller is similar to that of a standard 8051. there are two separate memory spaces: program memory and data memory. program and data memory share the same address space but are accessed via different instruction types. the memory organization of the c8051f336/7/8/9 device family is shown in figure 13.1 program/data memory (flash) (direct and indirect addressing) 0x00 0x7f upper 128 ram (indirect addressing only) 0x80 0xff special function register's (direct addressing only) data memory (ram) general purpose registers 0x1f 0x20 0x2f bit addressable lower 128 ram (direct and indirect addressing) 0x30 internal data address space external data address space xram - 512 bytes (accessable using movx instruction) 0x0000 0x01ff same 512 bytes as from 0x0000 to 0x01ff, wrapped on 512-byte boundaries 0x0200 0xffff 16 k flash (in-system programmable in 512 byte sectors) 0x0000 reserved 0x3e00 0x3dff figure 13.1. c8051f33 6/7/8/9 memory map
c8051f336/7/8/9 82 rev. 0.2 13.1. program memory the cip-51 core has a 64 kb program memory space. the c8051f336/7/8/9 implements 16 kb of this pro - gram memory space as in-system, re-programmable flash memory, organized in a contiguous block from addresses 0x0000 to 0x3dff. the address 0x3dff serves as the security lock byte for the device, and addresses above 0x3dff are reserved. lock byte 0x0000 0x3dff 0x3dfe 0x3e00 flash memory organized in 512-byte pages 0x3c00 flash memory space lock byte page 0x3fff reserved area figure 13.2. flash program memory map 13.1.1. movx instruction and program memory the movx instruction in an 8051 device is typica lly used to access external data memory. on the c8051f336/7/8/9 devices, the movx instruction is norma lly used to read and write on-chip xram, but can be re-configured to write and erase on-chip flash memo ry space. movc instructions are always used to read flash memory, while movx write instructions are used to erase an d write flash. this flash access feature provides a mechanism for the c8051f336/7/8/9 to update program code and use the program memory space for non-volatile data storage. refer to section ?16. flash memory? on page 98 for further details.
rev. 0.2 83 c8051f336/7/8/9 13.2. data memory the c8051f336/7/8/9 device family includes 768 bytes of ram data memory. 256 bytes of this memory is mapped into the internal ram space of the 8051. 512 bytes of this memory is on-chip ?external? memory. the data memory map is shown in figure 13.1 for reference. 13.2.1. internal ram there are 256 bytes of internal ram mapped into the data memory space from 0x00 through 0xff. the lower 128 bytes of data memory are used for general pu rpose registers and scratch pad memory. either direct or indirect addressing may be used to access the lower 128 bytes of data memory. locations 0x00 through 0x1f are addressable as four banks of gene ral purpose registers, each bank consisting of eight byte-wide registers. the next 16 bytes, locations 0x20 through 0x2f, ma y either be addressed as bytes or as 128 bit locations accessible with the direct addressing mode. the upper 128 bytes of data memory are accessible only by i ndirect addressing. this region occupies the same address space as the special function regist ers (sfr) but is physically separate from the sfr space. the addressing mode used by an instructio n when accessing locations above 0x7f determines whether the cpu accesses the upper 128 bytes of data memory space or th e sfrs. instructions that use direct addressing will access the sfr space. instructions using indirect addressing above 0x7f access the upper 128 bytes of data memory. figure 13.1 illustrates the data memo ry organization of the c8051f336/7/8/9. 13.2.1.1.general purpose registers the lower 32 bytes of data memory, locations 0x00 through 0x1f, may be addressed as four banks of gen - eral-purpose registers. each bank consists of eigh t byte-wide registers designated r0 through r7. only one of these banks may be enabled at a time. two bi ts in the program status word, rs0 (psw.3) and rs1 (psw.4), select the active register bank (see description of the psw in sfr definition 12.6 ). this allows fast context switching when entering subroutines and in terrupt service routines. indirect addressing modes use registers r0 and r1 as index registers. 13.2.1.2.bit addressable locations in addition to direct access to data memory organized as bytes, the sixteen data memory locations at 0x20 through 0x2f are also accessible as 128 individually addressable bits. each bit has a bit address from 0x00 to 0x7f. bit 0 of the byte at 0x20 has bit address 0x00 while bit7 of the byte at 0x20 has bit address 0x07. bit 7 of the byte at 0x2f has bit address 0x7f. a bit access is distinguished from a full byte access by the type of instruction used (bit source or destinat ion operands as opposed to a byte source or destina - tion). the mcs-51? assembly language allows an alternate notation for bit addressing of the form xx.b where xx is the byte address and b is the bit position within the byte. for example, the instruction: mov c, 22.3h moves the boolean value at 0x13 (bit 3 of the byte at location 0x22) into the carry flag.
c8051f336/7/8/9 84 rev. 0.2 13.2.1.3.stack a programmer's stack can be located anywhere in the 256-byte data memory. the stack area is desig - nated using the stack pointer (sp) sfr. the sp will point to the last lo cation used. the next value pushed on the stack is placed at sp+1 and then sp is incremen ted. a reset initializes the stack pointer to location 0x07. therefore, the first value pushed on the stack is placed at location 0x08, which is also the first regis - ter (r0) of register bank 1. thus, if more than one register bank is to be used, the sp should be initialized to a location in the data memory not being used for data storage. the stack depth can extend up to 256 bytes. 13.2.2. external ram there are 512 bytes of on-chip ram mapped into the external data memory space. all of these address locations may be accessed using the external move instruction (movx) and the data pointer (dptr), or using movx indirect addressing mode. if the movx in struction is used with an 8-bit address operand (such as @r1), then the high byte of the 16-bit addr ess is provided by the external memory interface con - trol register (emi0cn as shown in sfr definition 13.1 ). note: the movx instruction is also used for writes to the flash memory. see section ?16. flash memory? on page 98 for details. the movx instruction accesses xram by default. for a 16-bit movx operation (@dptr), the upper 7 bits of the 16-bit external data memory address word are "don't cares". as a result, the 512-byte ram is mapped modulo style over the entire 64 k external data memory address range. for example, the xram byte at address 0x0000 is shadowed at addresses 0x0200, 0x0400, 0x0600, 0x0800, etc. this is a useful feature when perf orming a linear memory fill, as the address pointer doesn't have to be reset when reaching the ram block boundary. sfr definition 13.1. emi0cn: external memory interface control bit 7 6 5 4 3 2 1 0 name pgsel type r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 sfr address = 0xaa bit name function 7:1 unused unused. read = 0000000b; write = don?t care 0 pgsel xram page select. the emi0cn register provides the high byte of the 16-bit external data memory address when using an 8-bit movx command, effectively selecting a 256-byte page of ram. since the upper (unused) bits of the register are always zero, the pgsel determines which page of xram is accessed. for example: if emi0cn = 0x01, addr esses 0x0100 through 0x01ff will be accessed.
rev. 0.2 85 c8051f336/7/8/9 14. special function registers the direct-access data memory locations from 0x80 to 0xff constitute the sp ecial function registers (sfrs). the sfrs provide control and data exchange with the c8051f336/7/8/9's resources and peripher - als. the cip-51 controller core duplicates the sfrs found in a typical 8051 implementation as well as implementing additional sfrs used to config ure and access the sub-systems unique to the c8051f336/7/8/9. this allo ws the addition of new functionality wh ile retaining compat ibility with the mcs- 51? instruction set. table 14.1 lists the sfrs implemented in the c8051f336/7/8/9 device family. the sfr registers are accessed anytime the direct ad dressing mode is used to access memory locations from 0x80 to 0xff. sfrs with addresses ending in 0x 0 or 0x8 (e.g. p0, tcon, scon0, ie, etc.) are bit- addressable as well as byte-addressable. all othe r sfrs are byte-addressable only. unoccupied addresses in the sfr space are rese rved for future use. accessing t hese areas will have an indeterminate effect and should be avoided. refer to the corres ponding pages of the data sheet, as indicated in ta b l e 14.2 , for a detailed description of each register. table 14.1. special function register (sfr) memory map f8 spi0cn pca0l pca0h pca0cpl0 pca0cph0 p0mat p0mask vdm0cn f0 b p0mdin p1mdin p2mdin eip1 pca0pwm e8 adc0cn pca0cpl1 pca0cph1 pca0cpl2 pca0cph2 p1mat p1mask rstsrc e0 acc xbr0 xbr1 osclcn it01cf eie1 smb0adm d8 pca0cn pca0md pca0cpm0 pca0cpm1 pca0cpm2 d0 psw ref0cn p0skip p1skip p2skip smb0adr c8 tmr2cn tmr2rll tmr2rlh tmr2l tmr2h c0 smb0cn smb0cf smb0dat adc0gtl adc0gth adc0ltl adc0lth b8 ip ida0cn amx0n amx0p adc0cf adc0l adc0h b0 oscxcn oscicn oscicl flscl flkey a8 ie clksel emi0cn a0 p2 spi0cfg spi0ckr spi0dat p0mdout p1mdout p2mdout 98 scon0 sbuf0 cpt0cn cpt0md cpt0mx 90 p1 tmr3cn tmr3rll tmr3rlh tmr3l tmr3h ida0l ida0h 88 tcon tmod tl0 tl1 th0 th1 ckcon psctl 80 p0 sp dpl dph pcon 0(8) 1(9) 2(a) 3(b) 4(c) 5(d) 6(e) 7(f) (bit addressable)
c8051f336/7/8/9 86 rev. 0.2 table 14.2. special function registers sfrs are listed in alphabetical order. all undefined sfr locations are reserved register address description page acc 0xe0 accumulator 79 adc0cf 0xbc adc0 configuration 48 adc0cn 0xe8 adc0 control 50 adc0gth 0xc4 adc0 greater-than compare high 51 adc0gtl 0xc3 adc0 greater-than compare low 51 adc0h 0xbe adc0 high 49 adc0l 0xbd adc0 low 49 adc0lth 0xc6 adc0 less-than compare word high 52 adc0ltl 0xc5 adc0 less-than compare word low 52 amx0n 0xba amux0 negative channel select 57 amx0p 0xbb amux0 positive channel select 56 b 0xf0 b register 79 ckcon 0x8e clock control 188 clksel 0xa9 clock select 117 cpt0cn 0x9b comparator0 control 68 cpt0md 0x9d comparator0 mode selection 69 cpt0mx 0x9f comparator0 mux selection 71 dph 0x83 data pointer high 78 dpl 0x82 data pointer low 78 eie1 0xe6 extended interrupt enable 1 94 eip1 0xf6 extended interrupt priority 1 95 emi0cn 0xaa external memory interface control 84 flkey 0xb7 flash lock and key 105 flscl 0xb6 flash scale 106 ida0cn 0xb9 current mode dac0 control 61 ida0h 0x97 current mode dac0 high 62 ida0l 0x96 current mode dac0 low 62 ie 0xa8 interrupt enable 92 ip 0xb8 interrupt priority 93 it01cf 0xe4 int0/int1 configuration 97 oscicl 0xb3 internal oscillator calibration 118 oscicn 0xb2 internal oscillator control 119 osclcn 0xe3 low-frequency o scillator control 120
rev. 0.2 87 c8051f336/7/8/9 oscxcn 0xb1 external oscillator control 122 p0 0x80 port 0 latch 138 p0mask 0xfe port 0 mask configuration 136 p0mat 0xfd port 0 match configuration 136 p0mdin 0xf1 port 0 input mode configuration 139 p0mdout 0xa4 port 0 output mode configuration 139 p0skip 0xd4 port 0 skip 140 p1 0x90 port 1 latch 140 p1mask 0xee port 1mask configuration 137 p1mat 0xed port 1 match configuration 137 p1mdin 0xf2 port 1 input mode configuration 141 p1mdout 0xa5 port 1 output mode configuration 141 p1skip 0xd5 port 1 skip 142 p2 0xa0 port 2 latch 142 p2mdin 0xf3 port 2 input mode configuration 143 p2mdout 0xa6 port 2 output mode configuration 143 p2skip 0xd6 port 2 skip 144 pca0cn 0xd8 pca control 223 pca0cph0 0xfc pca capture 0 high 228 pca0cph1 0xea pca capture 1 high 228 pca0cph2 0xec pca capture 2 high 228 pca0cpl0 0xfb pca capture 0 low 228 pca0cpl1 0xe9 pca capture 1 low 228 pca0cpl2 0xeb pca capture 2 low 228 pca0cpm0 0xda pca module 0 mode register 226 pca0cpm1 0xdb pca module 1 mode register 226 pca0cpm2 0xdc pca module 2 mode register 226 pca0h 0xfa pca counter high 227 pca0l 0xf9 pca counter low 227 pca0md 0xd9 pca mode 224 pca0pwm 0xf7 pca pwm configuration 225 pcon 0x87 power control 109 psctl 0x8f program store r/w control 104 psw 0xd0 program status word 80 table 14.2. special functi on registers (continued) sfrs are listed in alphabetical order. all undefined sfr locations are reserved register address description page
c8051f336/7/8/9 88 rev. 0.2 ref0cn 0xd1 voltage reference control 64 rstsrc 0xef reset source configuration/status 115 sbuf0 0x99 uart0 data buffer 172 scon0 0x98 uart0 control 171 smb0adm 0xe7 smbus slave address mask 156 smb0adr 0xd7 smbus slave address 156 smb0cf 0xc1 smbus configuration 151 smb0cn 0xc0 smbus control 153 smb0dat 0xc2 smbus data 157 sp 0x81 stack pointer 79 spi0cfg 0xa1 spi configuration 181 spi0ckr 0xa2 spi clock rate control 183 spi0cn 0xf8 spi control 182 spi0dat 0xa3 spi data 183 tcon 0x88 timer/counter control 193 th0 0x8c timer/counter 0 high 196 th1 0x8d timer/counter 1 high 196 tl0 0x8a timer/counter 0 low 195 tl1 0x8b timer/counter 1 low 195 tmod 0x89 timer/counter mode 194 tmr2cn 0xc8 timer/counter 2 control 200 tmr2h 0xcd timer/counter 2 high 202 tmr2l 0xcc timer/counter 2 low 201 tmr2rlh 0xcb timer/counter 2 reload high 201 tmr2rll 0xca timer/counter 2 reload low 201 tmr3cn 0x91 timer/counter 3control 206 tmr3h 0x95 timer/counter 3 high 208 tmr3l 0x94 timer/counter 3low 207 tmr3rlh 0x93 timer/counter 3 reload high 207 tmr3rll 0x92 timer/counter 3 reload low 207 vdm0cn 0xff v dd monitor control 113 xbr0 0xe1 port i/o crossbar control 0 134 xbr1 0xe2 port i/o crossbar control 1 135 table 14.2. special functi on registers (continued) sfrs are listed in alphabetical order. all undefined sfr locations are reserved register address description page
rev. 0.2 89 c8051f336/7/8/9 15. interrupts the c8051f336/7/8/9 includes an extended in terrupt system supporting a total of 14 interrupt sources with two priority levels. the allocation of interrupt sources between on-chip peripherals and external input pins varies according to the specific version of the device . each interrupt source ha s one or more associated interrupt-pending flag(s) located in an sfr. when a pe ripheral or external source meets a valid interrupt condition, the associated interrupt-pending flag is set to logic 1. if interrupts are enabled for the source, an interrupt req uest is generated when the interrupt-pending flag is set. as soon as execution of the current instructio n is complete, the cpu generates an lcall to a prede - termined address to begin execution of an interrupt se rvice routine (isr). each isr must end with an reti instruction, which returns program execution to the next instruction that would have been executed if the interrupt request had not occurred. if interrupts are not enabled, the interrupt-pending flag is ignored by the hardware and program execution continues as normal . (the interrupt-pending flag is set to logic 1 regard - less of the interrupt's enable/disable state.) each interrupt source can be individually enabled or disabled through the use of an associated interrupt enable bit in an sfr (ie?eie1). ho wever, interrupts must first be globally enabled by setting the ea bit (ie.7) to logic 1 before the individual interrupt enables are re cognized. setting the ea bit to logic 0 disables all interrupt sources regardless of the individual interrupt-enable settings. note: any instruction that clears a bit to disable an inte rrupt should be immediatel y followed by an instruc - tion that has two or more opcode bytes. using ea (global interrupt enable) as an example: // in 'c': for example, if an interrupt is posted during the exec ution phase of a "clr ea" opcode (or any instruction which clears a bit to disable an interrupt source), an d the instruction is followed by a single-cycle instruc - tion, the interrupt may be taken. however, a read of the enable bit will return a '0' inside the interrupt ser - vice routine. when the bit-clearing op code is followed by a multi-cycle in struction, the interrupt will not be taken. some interrupt-pending flags are automatically cleare d by the hardware when the cpu vectors to the isr. however, most are not cleared by the hardware and must be cleared by software before returning from the isr. if an interrupt-pending flag remains set after the cpu completes the return-from-interrupt (reti) instruction, a new interr upt request will be gen erated immediately and the cpu will re-enter the isr after the completion of the next instruction.
c8051f336/7/8/9 90 rev. 0.2 15.1. mcu interrupt sources and vectors the c8051f336/7/8/9 mcus support 14 interrupt source s. software can simulate an interrupt by setting any interrupt-pending flag to logic 1. if interrupts are enabl ed for the flag, an interr upt request will be gener - ated and the cpu will vector to th e isr address associated with the inte rrupt-pendi ng flag. mcu interrupt sources, associated vector ad dresses, priority order and control bits are summarized in ta b l e 15.1 . refer to the datasheet section associated with a particular on-chip peripheral for information regarding valid interrupt conditions for the peripheral and t he behavior of its interrupt-pending flag(s). 15.1.1. interrupt priorities each interrupt source can be individually programmed to one of two priority levels: low or high. a low prior - ity interrupt service routine can be pree mpted by a high priority interrupt. a high priority interrupt cannot be preempted. each interrupt has an associated interrupt priority bit in an sfr (ip or eip1) used to configure its priority level. low priority is th e default. if two interrupts are recognized simultaneously, the interrupt with the higher priority is serviced first. if both interrupts have the same priority level, a fixed priority order is used to arbitrate, given in ta b l e 15.1 . 15.1.2. interrupt latency interrupt response time depends on the state of the cpu when the interrupt occurs. pending interrupts are sampled and priority decoded each sys tem clock cycle. therefore, the fa stest possible response time is 5 system clock cycles: 1 clock cycle to detect the interrupt and 4 clock cycles to complete the lcall to the isr. if an interrupt is pending when a reti is execut ed, a single instruction is executed before an lcall is made to service the pending interrupt. therefore, the maximum response time for an interrupt (when no other interrupt is currently being serviced or the new in terrupt is of greater priority) occurs when the cpu is performing an reti instruct ion followed by a div as the next instructio n. in this case, th e response time is 18 system clock cycles: 1 clock cycle to detect the interrupt, 5 clock cycles to execute the reti, 8 clock cycles to complete the div instruction and 4 clock cycles to execute the lcall to the isr. if the cpu is executing an isr for an interr upt with equal or higher pr iority, the new interrupt will not be serviced until the current isr completes, including the reti and following instruction.
table 15.1. interrupt summary interrupt source interrupt vector priority order pending flag bit addressable? cleared by hw? enable flag priority control reset 0x0000 to p none n/a n/a always enabled always highest external interrupt 0 (/int0) 0x0003 0 ie0 (tcon.1) y y ex0 (ie.0) px0 (ip.0) timer 0 overflow 0x000b 1 tf0 (tcon.5) y y et0 (ie.1) pt0 (ip.1) external interrupt 1 (/int1) 0x0013 2 ie1 (tcon.3) y y ex1 (ie.2) px1 (ip.2) timer 1 overflow 0x001b 3 tf1 (tcon.7) y y et1 (ie.3) pt1 (ip.3) uart0 0x0023 4 ri0 (scon0.0) ti0 (scon0.1) y n es0 (ie.4) ps0 (ip.4) timer 2 overflow 0x002b 5 tf2h (tmr2cn.7) tf2l (tmr2cn.6) y n et2 (ie.5) pt2 (ip.5) spi0 0x0033 6 spif (spi0cn.7) wcol (spi0cn.6) modf (spi0cn.5) rxovrn (spi0cn.4) y n espi0 (ie.6) pspi0 (ip.6) smb0 0x003b 7 si (smb0cn.0) y n esmb0 (eie1.0) psmb0 (eip1.0) port match 0x0043 8 none n/a n/a emat (eie1.1) pmat (eip1.1) adc0 window compare 0x004b 9 ad0wint (adc0cn.3) y n ewadc0 (eie1.2) pwadc0 (eip1.2) adc0 conversion complete 0x0053 10 ad0int (adc0cn.5) y n eadc0 (eie1.3) padc0 (eip1.3) programmable counter array 0x005b 11 cf (pca0cn.7) ccfn (pca0cn.n) covf (pca0pwm.6) y n epca0 (eie1.4) ppca0 (eip1.4) comparator0 0x0063 12 cp0fif (cpt0cn.4) cp0rif (cpt0cn.5) n n ecp0 (eie1.5) pcp0 (eip1.5) reserved 0x006b 13 n/a n/a n/a n/a n/a timer 3 overflow 0x0073 14 tf3h (tmr3cn.7) tf3l (tmr3cn.6) n n et3 (eie1.7) pt3 (eip1.7) rev. 0.2 91 c8051f336/7/8/9 15.2. interrupt register descriptions the sfrs used to enable the interrupt sources and set their priority level are described in this section. refer to the data sheet section associated with a pa rticular on-chip peripheral for information regarding valid interrupt conditions for the peripheral and the behavior of its interrupt-pending flag(s).
sfr definition 15.1. ie: interrupt enable bit 7 6 5 4 3 2 1 0 name ea espi0 et2 es0 et1 ex1 et0 ex0 type r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 c8051f336/7/8/9 92 rev. 0.2 sfr address = 0xa8; bit-addressable bit name function 7 ea enable all interrupts. globally enables/disables all interrupts. it ov errides individual interrupt mask settings. 0: disable all interrupt sources. 1: enable each interrupt according to its individual mask setting. 6 espi0 enable serial peripheral interface (spi0) interrupt. this bit sets the masking of the spi0 interrupts. 0: disable all spi0 interrupts. 1: enable interrupt requests generated by spi0. 5 et2 enable timer 2 interrupt. this bit sets the masking of the timer 2 interrupt. 0: disable timer 2 interrupt. 1: enable interrupt requests generated by the tf2l or tf2h flags. 4 es0 enable uart0 interrupt. this bit sets the masking of the uart0 interrupt. 0: disable uart0 interrupt. 1: enable uart0 interrupt. 3 et1 enable timer 1 interrupt. this bit sets the masking of the timer 1 interrupt. 0: disable all timer 1 interrupt. 1: enable interrupt requests generated by the tf1 flag. 2 ex1 enable external interrupt 1. this bit sets the masking of external interrupt 1. 0: disable external interrupt 1. 1: enable interrupt requests generated by the /int1 input. 1 et0 enable timer 0 interrupt. this bit sets the masking of the timer 0 interrupt. 0: disable all timer 0 interrupt. 1: enable interrupt requests generated by the tf0 flag. 0 ex0 enable external interrupt 0. this bit sets the masking of external interrupt 0. 0: disable external interrupt 0. 1: enable interrupt requests generated by the /int0 input.
sfr definition 15.2. ip: interrupt priority bit 7 6 5 4 3 2 1 0 name type r r/w r/w r/w r/w r/w r/w r/w reset 1 0 0 0 0 0 0 0 rev. 0.2 93 c8051f336/7/8/9 sfr address = 0xb8; bit-addressable bit name function 7 unused unused. read = 1, write = don't care. 6 pspi0 serial peripheral interface (spi 0) interrupt priority control. this bit sets the priority of the spi0 interrupt. 0: spi0 interrupt set to low priority level. 1: spi0 interrupt set to high priority level. 5 pt2 timer 2 interrupt priority control. this bit sets the priority of the timer 2 interrupt. 0: timer 2 interrupt set to low priority level. 1: timer 2 interrupt set to high priority level. 4 ps0 uart0 interrupt priority control. this bit sets the priority of the uart0 interrupt. 0: uart0 interrupt set to low priority level. 1: uart0 interrupt set to high priority level. 3 pt1 timer 1 interrupt priority control. this bit sets the priority of the timer 1 interrupt. 0: timer 1 interrupt set to low priority level. 1: timer 1 interrupt set to high priority level. 2 px1 external interrupt 1 priority control. this bit sets the priority of the external interrupt 1 interrupt. 0: external interrupt 1 se t to low priority level. 1: external interrupt 1 se t to high priority level. 1 pt0 timer 0 interrupt priority control. this bit sets the priority of the timer 0 interrupt. 0: timer 0 interrupt set to low priority level. 1: timer 0 interrupt set to high priority level. 0 px0 external interrupt 0 priority control. this bit sets the priority of the external interrupt 0 interrupt. 0: external interrupt 0 se t to low priority level. 1: external interrupt 0 se t to high priority level. pspi0 pt2 ps0 pt1 px1 pt0 px0
sfr definition 15.3. eie1: extended interrupt enable 1 bit 7 6 5 4 3 2 1 0 name et3 reserved ecp0 epca0 eadc0 ewadc0 emat esmb0 type r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 c8051f336/7/8/9 94 rev. 0.2 sfr address = 0xe6 bit name function 7 et3 enable timer 3 interrupt. this bit sets the masking of the timer 3 interrupt. 0: disable timer 3 interrupts. 1: enable interrupt requests generated by the tf3l or tf3h flags. 6 reserved reserved. must write 0. 5 ecp0 enable comparator0 (cp0) interrupt. this bit sets the masking of the cp0 interrupt. 0: disable cp0 interrupts. 1: enable interrupt requests generated by the cp0rif or cp0fif flags. 4 epca0 enable programmable counte r array (pca0) interrupt. this bit sets the masking of the pca0 interrupts. 0: disable all pc a0 interrupts. 1: enable interrupt requests generated by pca0. 3 eadc0 enable adc0 conversion complete interrupt. this bit sets the masking of the adc0 conversion complete interrupt. 0: disable adc0 conversi on complete interrupt. 1: enable interrupt requests generated by the ad0int flag. 2 ewadc0 enable window comparison adc0 interrupt. this bit sets the masking of adc0 window comparison interrupt. 0: disable adc0 window comparison interrupt. 1: enable interrupt requests generated by adc0 window compare flag (ad0wint). 1 emat enable port match interrupts. this bit sets the masking of the port match event interrupt. 0: disable all port match interrupts. 1: enable interrupt requests generated by a port match. 0 esmb0 enable smbus (smb0) interrupt. this bit sets the masking of the smb0 interrupt. 0: disable all smb0 interrupts. 1: enable interrupt requests generated by smb0.
sfr definition 15.4. eip1: extended interrupt priority 1 bit 7 6 5 4 3 2 1 0 name pt3 reserved pcp0 ppca0 padc0 pwadc0 pmat psmb0 type r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 rev. 0.2 95 c8051f336/7/8/9 sfr address = 0xf6 bit name function 7 pt3 timer 3 interrupt priority control. this bit sets the priority of the timer 3 interrupt. 0: timer 3 interrupts set to low priority level. 1: timer 3 interrupts set to high priority level. 6 reserved reserved. must write 0. 5 pcp0 comparator0 (cp0) interru pt priority control. this bit sets the priority of the cp0 interrupt. 0: cp0 interrupt set to low priority level. 1: cp0 interrupt set to high priority level. 4 ppca0 programmable counter array (pca0) interrupt priority control. this bit sets the priority of the pca0 interrupt. 0: pca0 interrupt set to low priority level. 1: pca0 interrupt set to high priority level. 3 padc0 adc0 conversion complete interrupt priority control. this bit sets the priority of the adc0 conversion complete interrupt. 0: adc0 conversion complete inte rrupt set to low priority level. 1: adc0 conversion complete interrupt set to high priority level. 2 pwadc0 adc0 window comparator interrupt priority control. this bit sets the priority of the adc0 window interrupt. 0: adc0 window interrupt se t to low priority level. 1: adc0 window interrupt set to high priority level. 1 pmat port match interrupt priority control. this bit sets the priority of the port match event interrupt. 0: port match interrupt se t to low priority level. 1: port match interrupt se t to high priority level. 0 psmb0 smbus (smb0) interrupt priority control. this bit sets the priority of the smb0 interrupt. 0: smb0 interrupt set to low priority level. 1: smb0 interrupt set to high priority level.
c8051f336/7/8/9 96 rev. 0.2 15.3. external interrupts /int0 and /int1 the /int0 and /int1 external interrupt sources are confi gurable as active high or low, edge or level sensi - tive. the in0pl (/int0 polarity) and in1pl (/int1 polarity ) bits in the it01cf register select active high or active low; the it0 and it1 bits in tcon ( section ?24.1. timer 0 and timer 1? on page 189 ) select level or edge sensitive. the table below lis ts the possible configurations. active low, edge sensitive active low, edge sensitive active high, edge sensitive active high, edge sensitive active low, level sensitive active low, level sensitive active high, level sensitive active high, level sensitive /int0 and /int1 are assigned to port pins as defined in the it01cf register (see sfr definition 15.5). note that /int0 and /int0 port pin assignments are independent of any crossbar assignments. /int0 and /int1 will monitor their assigned port pins without disturbing th e peripheral that was assigned the port pin via the crossbar. to assign a port pin only to /int 0 and/or /int1, configure the crossbar to skip the selected pin(s). this is accomplished by setting the associated bit in register xbr0 (see section ?20.3. priority crossbar decoder? on page 131 for complete details on configuring the crossbar). ie0 (tcon.1) and ie1 (tcon.3) serve as the interr upt-pending flags for the /int0 and /int1 external interrupts, respectively. if an /int0 or /int1 external interrupt is configured as edge-sensitive, the corre - sponding interrupt-pending flag is automatically clear ed by the hardware when the cpu vectors to the isr. when configured as level sensitive, the interrupt-pendi ng flag remains logic 1 while the input is active as defined by the corresponding polarity bit (in0pl or in 1pl); the flag remains logi c 0 while the input is inac - tive. the external interrupt source must hold the input active until the interrupt request is recognized. it must then deactivate the interrup t request before execution of the isr completes or another interrupt request will be generated. it0 in0pl /int0 interrupt it1 in1pl /int1 interrupt 10 10 11 11 00 00 01 01
sfr definition 15.5. it01cf: int0/int1 configuration bit 7 6 5 4 3 2 1 0 name in1pl in1sl[2:0] in0pl in0sl[2:0] type r/w r/w r/w r/w reset 0 0 0 0 0 0 0 1 rev. 0.2 97 c8051f336/7/8/9 sfr address = 0xe4 bit name function 7 in1pl /int1 polarity. 0: /int1 input is active low. 1: /int1 input is active high. 6:4 in1sl[2:0] /int1 port pin selection bits. these bits select which port pin is assigned to /int1. note that this pin assignment is independent of the cr ossbar; /int1 will monitor the as signed port pi n without disturb - ing the peripheral that has been assigned t he port pin via the crossbar. the crossbar will not assign the port pin to a peripheral if it is configured to skip the selected pin. 000: select p0.0 001: select p0.1 010: select p0.2 011: select p0.3 100: select p0.4 101: select p0.5 110: select p0.6 111: select p0.7 3 in0pl /int0 polarity. 0: /int0 input is active low. 1: /int0 input is active high. 2:0 in0sl[2:0] /int0 port pin selection bits. these bits select which port pin is assigned to /int0. note that this pin assignment is independent of the cr ossbar; /int0 will monitor the as signed port pi n without disturb - ing the peripheral that has been assigned t he port pin via the crossbar. the crossbar will not assign the port pin to a peripheral if it is configured to skip the selected pin. 000: select p0.0 001: select p0.1 010: select p0.2 011: select p0.3 100: select p0.4 101: select p0.5 110: select p0.6 111: select p0.7
c8051f336/7/8/9 98 rev. 0.2 16. flash memory on-chip, re-programmable flash memory is included fo r program code and non-volatile data storage. the flash memory can be programmed in-system, a single by te at a time, through the c2 interface or by soft - ware using the movx instructio n. once cleared to logic 0, a flash bit must be erased to set it back to logic 1. flash bytes would typically be erased (set to 0xff) before being reprogrammed. the write and erase operations are automatically timed by hardware for proper execut ion; data polling to determine the end of the write/erase oper ation is not required. code execution is stalled during a flash write/erase oper - ation. refer to ta b l e 6.5 for complete flash memory electrical characteristics. 16.1. programming the flash memory the simplest means of programming the flash memory is through the c2 interface using programming tools provided by silicon labs or a third party vendor. this is the only means for programming a non-initial - ized device. for details on the c2 commands to program flash memory, see section ?26. c2 interface? on page 229 . to ensure the integrity of flash contents, it is strongly recommended that the on-chip v dd monitor be enabled in any system that includes code that writes and/or erases flash memory from soft - ware. see section 16.4 for more details. 16.1.1. flash lock and key functions flash writes and erases by user so ftware are protected with a lock and key function. th e flash lock and key register (flkey) must be writ ten with the correct key codes, in sequence, be fore flash operations may be performed. the key codes are: 0xa5, 0xf1. the timing does not matter, but the codes must be written in order. if the key codes are written out of or der, or the wrong codes are written, flash writes and erases will be disabled until the next system reset. flash writes and eras es will also be disabled if a flash write or erase is attempted before the key codes have been written properly. the flash lock resets after each write or erase; the key codes must be writte n again before a following flash operation can be per - formed. the flkey regist er is detailed in sfr definition 16.2 . 16.1.2. flash erase procedure the flash memory can be programmed by software using the movx write instru ction with the address and data byte to be programmed provided as normal ope rands. before writing to flash memory using movx, flash write operations must be enabled by: (1) setting the pswe program store write enable bit (psctl.0) to logic 1 (this directs the movx writes to target fl ash memory); and (2) writing the flash key codes in sequence to the flash lock register (flkey). the pswe bit remains set until cleared by soft - ware. a write to flash memory can clear bits to logic 0 but cannot set them; only an erase operation can set bits to logic 1 in flash. a byte location to be programmed should be erased before a new value is written. the flash memory is organized in 512-byte pages. the erase operation applies to an entire page (setting all bytes in the page to 0xff). to erase an en tire 512-byte page, perform the following steps: step 1. disable interrupts (recommended). step 2. set thepsee bit (register psctl). step 3. set the pswe bit (register psctl). step 4. write the first key code to flkey: 0xa5. step 5. write the second key code to flkey: 0xf1. step 6. using the movx instruction, write a data byte to any location within the 512-byte page to be erased. step 7. clear the pswe and psee bits.
rev. 0.2 99 c8051f336/7/8/9 16.1.3. flash write procedure flash bytes are programmed by software with the following sequence: step 1. disable interrupts (recommended). step 2. erase the 512-byte flash page containing the target location, as described in section 16.1.2. step 3. set the pswe bit (register psctl). step 4. clear the psee bit (register psctl). step 5. write the first key code to flkey: 0xa5. step 6. write the second key code to flkey: 0xf1. step 7. using the movx instruction, write a single data byte to the desired location within the 512- byte sector. step 8. clear the pswe bit. steps 5?7 must be repeated for each byte to be written. after flash writes are complete, pswe should be cleared so that movx instructions do not target program memory. 16.2. non-volatile data storage the flash memory can be used for non-volatile data storage as well as program code. this allows data such as calibration coefficients to be calculated and stored at run time. data is written using the movx write instruction and read using the movc instructi on. note: movx read instructions always target xram.
c8051f336/7/8/9 100 rev. 0.2 16.3. security options the cip-51 provides security options to protect the flash memory from inadvertent modification by soft - ware as well as to prevent the viewing of proprietary program code and constants. the program store write enable (bit pswe in register psctl) and the program store erase enable (bit psee in register psctl) bits protect the flash memory from accidental modification by software. pswe must be explicitly set to ?1? before software can modify the flash me mory; both pswe and psee must be set to ?1? before software can erase flash memory. additional security features prevent proprietary program code and data constants from being read or altered across the c2 interface. a security lock byte located at the last byte of fl ash user space offers protection of the flash program memory from access (reads, writes, or erases) by unpr otected code or the c2 inte rface. the flash security mechanism allows the user to lock n 512-byte flash pages, starting at page 0 (addresses 0x0000 to 0x01ff), where n is the 1?s complement number represented by the security lock byte. note that the page containing the flash security lock byte is unlocked when no other flash pages are locked (all bits of the lock byte are ?1?) and locked when any other flash pages are locked (any bit of the lock byte is ?0?). see example in figure 16.1 . lock byte page locked flash pages access limit set according to the flash security lock byte lock byte reserved area unlocked flash pages locked when any other flash pages are locked security lock byte: 11111101b 1s complement: 00000010b flash pages locked: 3 (first two flash pages + lock byte page) figure 16.1. flash program memory map
rev. 0.2 101 c8051f336/7/8/9 the level of flash security depends on the flash ac cess method. the three flash access methods that can be restricted are reads, writes, an d erases from the c2 debug interface, user firmware executing on unlocked pages, and user firmware executing on locked pages. ta b l e 16.1 summarizes the flash security features of the c8051f336/7/8/9 devices. table 16.1. flash security summary action c2 debug interface user firmware executing from: an unlocked page a locked page read, write or erase unlocked pages (except page with lock byte) permitted permitted permitted read, write or erase locked pages (except page with lock byte) not permitted flash error reset permitted read or write page containing lock byte (if no pages are locked) permitted permitted permitted read or write page containing lock byte (if any page is locked) not permitted flash error reset permitted read contents of lock byte (if no pages are locked) permitted permitted permitted read contents of lock byte (if any page is locked) not permitted flash error reset permitted erase page containing lock byte (if no pages are locked) permitted flash error reset flash error reset erase page containing lock byte?unlock all pages (if any page is locked) c2 device erase only flash error reset flash error reset lock additional pages (change '1's to '0's in the lock byte) not permitted flash error reset flash error reset unlock individual pages (change '0's to '1's in the lock byte) not permitted flash error reset flash error reset read, write or erase reserved area not permitted flash error reset flash error reset c2 device erase - erases all flash pages in cluding the page containing the lock byte. flash error reset - not permitted; causes flash erro r device reset (ferror bit in rstsrc is '1' after reset). - all prohibited operations that are performed via the c2 interface are ignored (do not cause device reset). - locking any flash page also locks th e page containing the lock byte. - once written to, the lock byte cannot be modifi ed except by performing a c2 device erase. - if user code writes to the lock byte, the lock does not take effect until the next device reset.
c8051f336/7/8/9 102 rev. 0.2 16.4. flash write and erase guidelines any system which contains routines which write or er ase flash memory from software involves some risk that the write or erase ro utines will execute unin tentionally if the cpu is op erating outside its specified operating range of v dd , system clock frequency, or temperature. this accidental execution of flash modi - fying code can result in alteration of flash memory contents causing a system failure that is only recover - able by re-flashing the code in the device. the following guidelines are recommended for any syst em which contains routin es which write or erase flash from code. 16.4.1. v dd maintenance and the v dd monitor 1. if the system power supply is subject to volta ge or current "spikes," add sufficient transient protection devices to the power supply to ensure that the supply voltages listed in the absolute maximum ratings table are not exceeded. 2. make certain that the minimum v dd rise time specification of 1 ms is met. if the system cannot meet this rise time specification, then add an external v dd brownout circuit to the rst pin of the device that holds the device in reset until v dd reaches 2.7 v and re-asserts rst if v dd drops below 2.7 v. 3. enable the on-chip v dd monitor and enable the v dd monitor as a reset source as early in code as possible. this should be the first set of inst ructions executed after the reset vector. for 'c'- based systems, this will involve modifying the st artup code added by the 'c' compiler. see your compiler documentation for more details. make certain that there are no delays in software between enabling the v dd monitor and enabling the v dd monitor as a reset source. code examples showing this can be found in ?an201: writing to flash from firmware", available from the silicon laboratories web site. 4. as an added precaution, explicitly enable the v dd monitor and enable the v dd monitor as a reset source inside the functions that write and erase flash memory. the v dd monitor enable instructions should be placed just after the in struction to set pswe to a '1', but before the flash write or erase operation instruction. 5. make certain that all writes to the rstsrc (r eset sources) register use direct assignment operators and explicitly do not use the bit- wise operators (such as and or or). for exam - ple, "rstsrc = 0x02" is correct. "rstsrc |= 0x02" is incorrect. 6. make certain that all writes to the rstsrc regist er explicitly set the porsf bit to a '1'. areas to check are initialization code which enables ot her reset sources, such as the missing clock detector or comparator, for example, and instru ctions which force a so ftware reset. a global search on "rstsrc" can quickly verify this. 16.4.2. pswe maintenance 7. reduce the number of places in code where the pswe bit (b0 in psctl) is set to a '1'. there should be exactly one routine in code that sets pswe to a '1' to write flash bytes and one rou - tine in code that sets pswe and psee bo th to a '1' to erase flash pages. 8. minimize the number of variable accesses while pswe is set to a '1'. handle pointer address updates and loop variable maintenance outsi de the "pswe = 1;... pswe = 0;" area. code examples showing this can be found in an201, "writing to flash from firmware" , available from the silicon laboratories web site. 9. disable interrupts prior to setti ng pswe to a '1' and leave them disabled until after pswe has been reset to '0'. any interrup ts posted during the flash writ e or erase operation will be ser -
rev. 0.2 103 c8051f336/7/8/9 viced in priority order after the flash operation has been completed and interrupts have been re-enabled by software. 10. make certain that the flash write and erase pointer variables are not located in xram. see your compiler documentation for instructions regard ing how to explicitly lo cate variables in dif - ferent memory areas. 11. add address bounds checking to the routines th at write or erase flash memory to ensure that a routine called with an illegal address does not re sult in modification of the flash. 16.4.3. system clock 12. if operating from an external crystal, be advised that crystal performance is susceptible to electrical interference and is sensitive to layout and to changes in temperature. if the system is operating in an electrically noi sy environment, use the internal oscillator or use an external cmos clock. 13. if operating from the ex ternal oscillator, switch to the internal oscillator during flash write or erase operations. the external oscillator can continue to run, and the cpu can switch back to the external oscillator after th e flash operation has completed. additional flash recommendations and example code can be found in an201, "writing to flash from firm - ware" , available from the silic on laboratories web site.
sfr definition 16.1. psctl: program store r/w control bit 7 6 5 4 3 2 1 0 name psee pswe type r r r r r r r/w r/w reset 0 0 0 0 0 0 0 0 c8051f336/7/8/9 104 rev. 0.2 sfr address = 0x8f bit name function 7:2 unused unused. read = 000000b, write = don?t care. 1 psee program store erase enable setting this bit (in combination with pswe) allows an entire page of flash program memory to be erased. if this bit is logic 1 and flash writes are enabled (pswe is logic 1), a write to flash memory using the movx instruction will erase the entire page that contains the location addressed by the movx instruction. the value of the data byte written does not matter. 0: flash program memory erasure disabled. 1: flash program memory erasure enabled. 0 pswe program store write enable setting this bit allows writing a byte of data to the flash program memory using the movx write instruction. the flash location should be erased before writing data. 0: writes to flash program memory disabled. 1: writes to flash program memory enabl ed; the movx write instruction targets flash memory.
sfr definition 16.2. flkey: flash lock and key bit 7 6 5 4 3 2 1 0 name flkey[7:0] type r/w reset 0 0 0 0 0 0 0 0 rev. 0.2 105 c8051f336/7/8/9 sfr address = 0xb7 bit name function 7:0 flkey[7:0] flash lock and key register. write: this register provides a lock and key func tion for flash erasures and writes. flash writes and erases ar e enabled by writing 0xa5 follo wed by 0xf1 to the flkey regis - ter. flash writes and erases are automatically disabled after the next write or erase is complete. if any writes to flkey are performed incorrectly, or if a flash write or erase operation is attempted while these operations are disa bled, the flash will be perma - nently locked from writes or erasures unt il the next device reset. if an application never writes to flash, it can intentionally lock the flash by writing a non-0xa5 value to flkey from software. read: when read, bits 1?0 indicate the current flash lock state. 00: flash is write/erase locked. 01: the first key code has been written (0xa5). 10: flash is unlocked (writes/erases allowed). 11: flash writes/erases disabled until the next reset.
sfr definition 16.3. flscl: flash scale bit 7 6 5 4 3 2 1 0 name type reset 1 0 0 0 0 0 0 0 c8051f336/7/8/9 106 rev. 0.2 sfr address = 0xb6 bit name function 7 fose flash one-shot enable this bit enables the flash read one-shot (recommended). if the flash one-shot is dis - abled, the flash sense amps are enabled for a full clock cycle during flash reads, increasing the device power consumption. 0: flash one-shot disabled. 1: flash one-shot enabled. 6:0 reserved reserved. must write 0000000b. fose reserved reserved reserved re served reserved reserved reserved r/w r/w r/w r/w r/w r/w r/w r/w
rev. 0.2 107 c8051f336/7/8/9 17. power management modes the c8051f336/7/8/9 devices have three software programmable power management modes: idle, stop, and suspend. idle mode and stop mode are part of the standard 8051 architecture, while suspend mode is an enhanced power-saving m ode implemented by the high -speed oscillator peripheral. idle mode halts the cpu while leavin g the peripherals and clocks active. in stop mode, the cpu is halted, all interrupts and timers (except the missing clock de tector) are inactive, and th e internal oscillator is stopped (analog peripherals remain in their se lected states; the external o scillator is not affected). sus - pend mode is similar to stop mode in that the internal oscillator an d cpu are halted, but the device can wake on events such as a port mismatch, comparator low output, or a timer 3 overflow. since clocks are running in idle mode, power consumption is dependent upon the system clock frequency and the number of peripherals left in active mode before entering idle. stop mode and suspend mode consume the least power because the majority of the device is shut down with no clocks active. sfr definition 17.1 describes the power control register (pcon) used to contro l the c8051f336/7/8/9's stop and idle power manage - ment modes. suspend mode is controlled by the suspend bit in the oscicn register ( sfr definition 19.3 ). although the c8051f336/7/8/9 has idle, stop, and sus pend modes available, more control over the device power can be achieved by enabling/disabling individ ual peripherals as needed. each analog peripheral can be disabled when not in use and placed in low power mode. digital peripherals, such as timers or serial buses, draw little power when they are not in use. turning off oscillators lowers power consumption considerably, at the expense of reduced functionality. 17.1. idle mode setting the idle mode select bit (pcon.0) causes the hardware to halt the cpu and enter idle mode as soon as the instruction that sets the bit completes execution. all internal registers and memory maintain their original data. all analog and digital peripherals can remain active during idle mode. idle mode is terminated when an enabled interrupt is asserted or a reset occurs. the assertion of an enabled interrupt will cause the idle mode selection bit (pcon.0) to be cleared and the cpu to resume operation. the pen ding interrupt will be serviced and the next in struction to be executed after the return from interrupt (reti) will be the instruction immedi ately following the one that se t the idle mode select bit. if idle mode is terminated by an internal or external reset, the cip-51 performs a normal reset sequence and begins program execution at address 0x0000. note: if the instructio n following the write of the idle bit is a sing le-byte instruction and an interrupt occurs during the execution phase of the instruction that sets the idle bit, the cpu may not wake from idle mode when a future interrupt occurs. therefore, instructi ons that set the idle bit should be followed by an instruction that has two or mo re opcode bytes, for example: // in ?c?: pcon |= 0x01; // set idle bit pcon = pcon; // ... followed by a 3-cycle dummy instruction ; in assembly: orl pcon, #01h ; set idle bit mov pcon, pcon ; ... followed by a 3-cycle dummy instruction if enabled, the watchdog timer (wdt) will eventually cause an internal watchdog reset and thereby termi - nate the idle mode. this feature protects the system from an unintended permanent shutdown in the event of an inadvertent write to the pcon register. if this behavior is not desired, th e wdt may be disabled by
c8051f336/7/8/9 108 rev. 0.2 software prior to entering the idle mo de if the wdt was initially configured to allow this operation. this pro - vides the opportunity for additional power savings, allo wing the system to remain in the idle mode indefi - nitely, waiting for an external stimulus to wake up the system. refer to section ?18.6. pca watchdog timer reset? on page 114 for more information on the use and configuration of the wdt. 17.2. stop mode setting the stop mode select bit (pcon.1) causes the co ntroller core to enter stop mode as soon as the instruction that sets the bit complete s execution. in stop mode the intern al oscillator, cpu, and all digital peripherals are stopp ed; the state of the external oscillator circ uit is not affected. ea ch analog peripheral (including the external oscillator circui t) may be shut down i ndividually prior to ente ring stop mode. stop mode can only be terminated by an internal or external reset. on reset, the device performs the normal reset sequence and begins program execution at address 0x0000. if enabled, the missing clock detect or will cause an internal reset and ther eby terminate th e stop mode. the missing clock detector should be disabled if the cpu is to be put to in stop mode for longer than the mcd timeout of 100 s. 17.3. suspend mode setting the suspend bit (oscicn.5) causes the hardware to halt the cpu and the high-frequency inter - nal oscillator, and go into suspend m ode as soon as the inst ruction that sets the bit completes execution. all internal registers and memory main tain their original data. most digital peripherals are not active in sus - pend mode. the exception to this is the port match feature and timer 3, when it is run from an external oscillator source or the inte rnal low-frequency oscillator. suspend mode can be terminated by four types of events, a port match (described in section ?20.5. port match? on page 136 ), a timer 3 overflow (described in section ?24.3. timer 3? on page 203 ), a comparator low output (if enabled), or a device reset event. note that in order to run timer 3 in suspend mode, the timer must be configured to clock fr om either the external clock source or the internal low-frequency oscil - lator source. when su spend mode is terminated, th e device will continue execution on the instruction fol - lowing the one that set the suspend bit. if the wake event (port match or timer 3 overflow) was configured to generate an interrupt, t he interrupt will be servic ed upon waking the device. if suspend mode is terminated by an internal or external reset, the cip-51 performs a normal reset sequence and begins program execution at address 0x0000.
sfr definition 17.1. pcon: power control bit 7 6 5 4 3 2 1 0 name gf[5:0] stop idle type r/w r/w r/w reset 0 0 0 0 0 0 0 0 rev. 0.2 109 c8051f336/7/8/9 sfr address = 0x87 bit name function 7:2 gf[5:0] general purpose flags 5?0. these are general purpose flags for use under software control. 1 stop stop mode select. setting this bit will place the cip-51 in st op mode. this bit will always be read as 0. 1: cpu goes into stop mode (internal oscillator stopped). 0 idle idle: idle mode select. setting this bit will place the cip-51 in idle mode. this bit will always be read as 0. 1: cpu goes into idle mode. (shuts off clo ck to cpu, but clock to timers, interrupts, serial ports, and analog peripherals are still active.)
c8051f336/7/8/9 110 rev. 0.2 18. reset sources reset circuitry allows the controller to be easily placed in a predefined default condition. on entry to this reset state, th e following occur: ? cip-51 halts program execution ? special function registers (sfrs) are initialized to their defined reset values ? external port pins are forced to a known state ? interrupts and timers are disabled. all sfrs are reset to the predefined values noted in the sfr detailed descriptions. the contents of internal data memory are unaffected during a reset; any prev iously stored data is preserved. however, since the stack pointer sfr is reset, the stack is effectively lo st, even though the data on the stack is not altered. the port i/o latches are reset to 0xff (all logic ones) in open-drain mode. weak pullups are enabled dur - ing and after the reset. for v dd monitor and power-on resets, the rst pin is driven low until the device exits the reset state. on exit from the reset state, the program counter (pc) is reset, and the system clock defaults to the inter - nal oscillator. the watchdog timer is enabled with the system clock divided by 12 as its clock source. pro - gram execution begins at location 0x0000. pca wdt missing clock detector (one- shot) (software reset) system reset reset funnel px.x px.x en swrsf system clock cip-51 microcontroller core extended interrupt handler en wdt enable mcd enable errant flash operation /rst (wired-or) power on reset '0' + - comparator 0 c0rsef vdd + - supply monitor enable figure 18.1. reset sources
rev. 0.2 111 c8051f336/7/8/9 18.1. power-on reset during power-up, the device is held in a reset state and the rst pin is driven low until v dd settles above v rst . a delay occurs before the device is released from reset; the delay decreases as the v dd ramp time increases (v dd ramp time is defined as how fast v dd ramps from 0 v to v rst ). figure 18.2 . plots the power-on and v dd monitor reset timing. the maximum v dd ramp time is 1 ms; slower ramp times may cause the device to be released from reset before v dd reaches the v rst level. for ramp times less than 1 ms, the power-on reset delay (t pordelay ) is typically less than 0.3 ms. on exit from a power-on reset, the porsf fl ag (rstsrc.1) is set by hardware to logic 1. when porsf is set, all of the other reset flags in the rstsrc regist er are indeterminate (porsf is cleared by all other resets). since all resets cause program execution to begin at the same location (0x0000) software can read the porsf flag to determine if a power-up was t he cause of reset. the content of internal data mem - ory should be assumed to be undefined after a power-on reset. the v dd monitor is enabled following a power-on reset. power-on reset vdd monitor reset /rst t volts 1.0 2.0 logic high logic low t pordelay v d d 2.70 2.55 v rst vdd figure 18.2. power-on and v dd monitor reset timing
c8051f336/7/8/9 112 rev. 0.2 18.2. power-fail reset / v dd monitor when a power-down transition or power irregularity causes v dd to drop below v rst , the power supply monitor will drive the rst pin low and hold the cip-51 in a reset state (see figure 18.2 ). when v dd returns to a level above v rst , the cip-51 will be released from the reset st ate. note that even though internal data memory contents are not altered by the power-fa il reset, it is impossib le to determine if v dd dropped below the level required for data retention. if the porsf flag reads ?1?, the data may no longer be valid. the v dd monitor is enabled after power-on resets. its defined st ate (enabled/disabled) is not altered by any other reset source. for example, if the v dd monitor is disabled by code and a software reset is performed, the v dd monitor will still be disabled after the reset. important note: if the v dd monitor is being turned on from a disabled state, it should be enabled before it is selected as a reset source. selecting the v dd monitor as a reset source before it is enabled and stabi - lized may cause a system reset. in some applications, this reset may be undesirable. if this is not desirable in the application, a delay should be introduced betwe en enabling the monitor and selecting it as a reset source. the procedure for enabling the v dd monitor and configuring it as a reset source from a disabled state is shown below: step 1. enable the v dd monitor (vdmen bit in vdm0cn = ?1?). step 2. if necessary, wait for the v dd monitor to stabilize (s ee table 6.4 for the v dd monitor turn- on time). step 3. select the v dd monitor as a reset source (porsf bit in rstsrc = ?1?). see figure 18.2 for v dd monitor timing; note that the power-on -reset delay is not incurred after a v dd monitor reset. see table 6.4 for complete electrical characteristics of the v dd monitor.
sfr definition 18.1. vdm0cn: v dd monitor control bit 7 6 5 4 3 2 1 0 name vdmen vddstat type r/w r r r r r r r reset varies varies 0 0 0 0 0 0 rev. 0.2 113 c8051f336/7/8/9 sfr address = 0xff bit name function 7 vdmen v dd monitor enable. this bit turns the v dd monitor circuit on/off. the v dd monitor cannot generate sys - tem resets until it is also selected as a reset source in register rstsrc ( sfr def - inition 18.2 ). selecting the v dd monitor as a reset source before it has stabilized may generate a system reset. in systems wher e this reset would be undesirable, a delay should be introduced between enabling the v dd monitor and selecting it as a reset source. see ta b l e 6.4 for the minimum v dd monitor turn-on time. 0: v dd monitor disabled. 1: v dd monitor enabled. 6 vddstat v dd status. this bit indicates the current power supply status (v dd monitor output). 0: v dd is at or below the v dd monitor threshold. 1: v dd is above the v dd monitor threshold. 5:0 unused unused. read = 000000b; write = don?t care. 18.3. external reset the external rst pin provides a means for external circuitry to force the device into a reset state. assert - ing an active-low signal on the rst pin generates a reset; an external pullup and/or decoupling of the rst pin may be necessary to avoid erroneous noise-induced resets. see ta b l e 6.4 for complete rst pin spec - ifications. the pinrsf flag (rstsrc.0) is set on exit from an external reset. 18.4. missing clock detector reset the missing clock detector (mcd) is a one-shot circuit that is triggered by the syst em clock. if the system clock remains high or low for more than 100 s, the one-shot will time out an d generate a reset. after a mcd reset, the mcdrsf flag (rstsrc.2) will read ?1?, signifying the mcd as the reset source; otherwise, this bit reads ?0?. writing a ?1? to the mcdrsf bit enables the missing clo ck detector; writing a ?0? disables it. the state of the rst pin is unaffected by this reset.
c8051f336/7/8/9 114 rev. 0.2 18.5. comparator0 reset comparator0 can be configured as a reset source by writing a ?1? to the c0rsef flag (rstsrc.5). comparator0 should be enabled and allowed to settle prior to writing to c0rsef to prevent any turn-on chatter on the output from generating an unwanted rese t. the comparator0 reset is active-low: if the non- inverting input voltage (on cp0+) is le ss than the inverting input voltage (on cp0-), the device is put into the reset state. afte r a comparator0 reset, the c0rsef flag (rstsrc.5) will read ?1? signifying comparator0 as the reset source; otherwise, this bit reads ?0?. the state of the rst pin is unaffected by this reset. 18.6. pca watchdog timer reset the programmable watchdog timer (wdt) function of the programmable counter array (pca) can be used to prevent software from running out of cont rol during a system malfunction. the pca wdt function can be enabled or disabled by software as described in section ?25.4. watchdog timer mode? on page 221 ; the wdt is enabled and clocked by sysclk / 12 following any reset. if a system malfunction prevents user software from updating the wdt, a re set is generated and the wdtrsf bit (rstsrc.5) is set to ?1?. the state of the rst pin is unaffected by this reset. 18.7. flash error reset if a flash read/write/era se or program read targets an illegal address, a system reset is generated. this may occur due to any of the following: ? a flash write or erase is attempted above user code space. this occurs when pswe is set to ?1? and a movx write operation targets an address above address 0x3dff. ? a flash read is attempted above user code space. this occurs when a movc operation targets an address above address 0x3dff. ? a program read is attempted above user code spac e. this occurs when user code attempts to branch to an address above 0x3dff. ? a flash read, write or erase attempt is re stricted due to a flash security setting (see section ?16.3. security options? on page 100 ). the ferror bit (rstsrc.6) is set following a flash error reset. the state of the rst pin is unaffected by this reset. 18.8. software reset software may force a reset by writ ing a ?1? to the swrsf bit (rstsrc.4). the swrsf bit will read ?1? fol - lowing a software forced reset. the state of the rst pin is unaffected by this reset.
sfr definition 18.2. rstsrc: reset source bit 7 6 5 4 3 2 1 0 name ferror c0rsef swrsf wdtrsf mcdrsf porsf pinrsf type r r r/w r/w r r/w r/w r reset 0 varies varies varies varies varies varies varies rev. 0.2 115 c8051f336/7/8/9 sfr address = 0xef bit name description write read 7 unused unused. don?t care. 0 6 ferror flash error reset flag. n/a set to ?1? if flash read/write/erase error caused the last reset. 5 c0rsef comparator0 reset enable and flag. writing a ?1? enables comparator0 as a reset source (active-low). set to ?1? if comparator0 caused the last reset. 4 swrsf software reset force and flag. writing a ?1? forces a sys - tem reset. set to ?1? if last reset was caused by a write to swrsf. 3 wdtrsf watchdog timer reset flag. n/a set to ?1? if watchdog timer overflow caused the last reset. 2 mcdrsf missing clock detector enable and flag. writing a ?1? enables the missing clock detector. the mcd triggers a reset if a missing clock condition is detected. set to ?1? if missing clock detector timeout caused the last reset. 1 porsf power-on / v dd monitor reset flag, and v dd monitor reset enable. writing a ?1? enables the v dd monitor as a reset source. writing ?1? to this bit before the v dd monitor is enabled and stabilized may cause a system reset. set to ?1? anytime a power- on or v dd monitor reset occurs. when set to ?1? all other rstsrc flags are inde - terminate. 0 pinrsf hw pin reset flag. n/a set to ?1? if rst pin caused the last reset. note: do not use read-modify-write operations on this register
c8051f336/7/8/9 116 rev. 0.2 19. oscillators and clock selection c8051f336/7/8/9 devices include a programmable internal high-frequency oscilla tor, a programmable internal low-freq uency oscillator, and an external oscillator dr ive circuit. the internal high-frequency oscilla - tor can be enabled/disabled and calibrated using the oscicn and oscicl re gisters, as shown in figure 19.1 . the internal low-frequency oscillator can be enabled/disabled and calibrated using the osclcn register. the system clock can be sourced by t he external oscillato r circuit or either internal oscil - lator. both internal oscillators of fer a selectable post-scaling feature. osc programmable internal clock generator input circuit en sysclk n oscicl oscicn ioscen ifrdy ifcn1 ifcn0 xtal1 xtal2 option 2 vdd xtal2 option 1 10m ? option 3 xtal2 option 4 xtal2 oscxcn xtlvld xoscmd2 xoscmd1 xoscmd0 xfcn2 xfcn1 xfcn0 clksel sel1 sel0 osclcn osclen osclrdy osclf3 osclf2 osclf1 osclf0 oscld1 oscld0 low frequency oscillator en n oscld osclf osclf oscld figure 19.1. oscillator options
rev. 0.2 117 c8051f336/7/8/9 19.1. system clock selection the clksl[1:0] bits in register cl ksel select which osc illator source is used as the system clock. clksl[1:0] must be set to 01b for the system clock to run from th e external oscillator; however the exter - nal oscillator may still clock certain per ipherals (timers, pca) when the inte rnal oscillator is selected as the system clock. the system clock may be switched on-the-fly be tween the intern al oscillator, external oscilla - tor, and clock multiplier so long as the selected clock source is enabled and has settled. the internal high-frequency and low-frequency oscillators require little start-up ti me and may be selected as the system clock immediately fo llowing the register writ e which enables the oscillator. the external rc and c modes also typically require no startup time. external crystals and ceramic resonato rs however, typically require a start-up time before they are settled and ready for use. the crystal valid flag (xtlvld in re gister oscxcn) is set to '1' by hardware when the external crystal or cera mic resonator is settled. in crystal mode, to avoid reading a false xtlvld, soft - ware should delay at least 1 ms between enabling the external oscillator and checking xtlvld. sfr definition 19.1. clksel: clock select bit 7 6 5 4 3 2 1 0 name clksl[1:0] type r r r r r r r/w reset 0 0 0 0 0 0 0 0 sfr address = 0xa9; bit name function 7:2 unused unused. read = 000000b; write = don?t care 1:0 clksl[1:0] system clock source select bits. 00: sysclk derived from the internal hig h-frequency oscillato r and scaled per the ifcn bits in register oscicn. 01: sysclk derived from the external oscillator circuit. 10: sysclk derived from the internal lo w-frequency oscillato r and scaled per the oscld bits in register osclcn. 11: reserved.
c8051f336/7/8/9 118 rev. 0.2 19.2. programmable internal hi gh-frequency (h-f) oscillator all c8051f336/7/8/9 devices include a programmable inte rnal high-frequency osc illator that defaults as the system clock after a system rese t. the internal oscillator period ca n be adjusted via the oscicl regis - ter as defined by sfr definition 19.2 . on c8051f336/7/8/9 device s, oscicl is factory ca librated to obtain a 24.5 mhz base frequency. note that the system clock may be deri ved from the programmed internal osc illator divided by 1, 2, 4, or 8, as defined by the ifcn bits in register oscicn. the divide value defaults to 8 following a reset. 19.2.1. internal oscillator suspend mode when software writes a logic 1 to suspend (oscicn. 5), the internal oscillato r is suspended. if the sys - tem clock is derived from t he internal oscillator, the input clock to the peripheral or cip-51 will be stopped until one of the following events occur: ? port 0 match event. ? port 1 match event. ? comparator 0 enabled and output is logic 0. ? timer3 overflow event. when one of the oscillator awakening events occur, the internal oscillato r, cip-51, and affe cted peripherals resume normal operation, regardless of whether the event also causes an interrupt. the cpu resumes execution at the instruction fo llowing the write to suspend. sfr definition 19.2. oscicl: internal h-f o scillator calibration bit 7 6 5 4 3 2 1 0 name oscicl[6:0] type r r/w reset 0 varies varies varies varies varies varies varies sfr address = 0xb3; bit name function 7 unused unused. read = 0; write = don?t care 6:0 oscicl[6:0] internal oscillator calibration bits. these bits determine the internal oscillato r period. when set to 0000000b, the h-f oscillator operates at its fa stest setting. when set to 111 1111b, the h-f oscillator operates at its slowest setting. the reset value is factory calibrated to generate an internal oscillator frequency of 24.5 mhz.
sfr definition 19.3. oscicn: internal h-f oscillator control bit 7 6 5 4 3 2 1 0 name ioscen ifrdy suspend stsync ifcn[1:0] type r/w r r/w r r r r/w reset 1 1 0 0 0 0 0 0 rev. 0.2 119 c8051f336/7/8/9 sfr address = 0xb2; bit name function 7 ioscen internal h-f oscillator enable bit. 0: internal h-f oscillator disabled. 1: internal h-f oscillator enabled. 6 ifrdy internal h-f oscillator frequency ready flag. 0: internal h-f oscillator is no t running at pr ogrammed frequency. 1: internal h-f oscillator is running at progr ammed frequency. 5 suspend internal oscillator suspend enable bit. setting this bit to logic 1 places the in ternal oscillator in suspend mode. the inter - nal oscillator resumes operation when one of the suspend mode awakening events occurs. 4 stsync suspend timer synchronization bit. this bit is used to indicate when it is sa fe to read and write the registers associated with the suspend wake-up timer ( see section 17.3 for suspend wake-up details). if a suspend wake-up source othe r than the timer has brou ght the oscillator out of suspend mode, it may take up to three timer clocks before the timer can be read or written. when stsync reads '1', reads and wr ites of the timer register should not be performed. when stsync reads '0', it is sa fe to read and write the timer registers. 3:2 unused unused. read = 00b; write = don?t care 1:0 ifcn[1:0] internal h-f oscillator fre quency divider control bits. 00: sysclk derived from internal h-f oscillator divided by 8. 01: sysclk derived from internal h-f oscillator divided by 4. 10: sysclk derived from internal h-f oscillator divided by 2. 11: sysclk derived from internal h-f oscillator divided by 1.
c8051f336/7/8/9 120 rev. 0.2 19.3. programmable internal low -frequency (l-f) oscillator all c8051f336/7/8/9 devices include a programmable low-fre quency internal oscillato r, which is calibrated to a nominal frequency of 80 khz. the low-frequency oscillator circ uit includes a divi der that can be changed to divide the clock by 1, 2, 4, or 8, using the oscld bits in the osclcn register (see sfr defi - nition 19.4 ). additionally, the osclf[3:0] bits can be used to adjust the oscilla tor?s output frequency. 19.3.1. calibrating the internal l-f oscillator timers 2 and 3 include capture func tions that can be used to capture the oscillato r frequency, when run - ning from a known time base. when either timer 2 or timer 3 is configured for l- f oscillator capture mode, a falling edge (timer 2) or rising edge (timer 3) of the low-frequency osc illator?s output will cause a capture event on the corresponding timer. as a capture event occurs, the current timer value (tmrnh:tmrnl) is copied into the timer reload re gisters (tmrnrlh:tmrnrll). by recording the differ - ence between two successive time r capture values, the lo w-frequency oscillator? s period can be calcu - lated. the osclf bits can then be adjusted to produce the desire d oscillator frequency. sfr definition 19.4. osclcn: internal l-f oscillator control bit 7 6 5 4 3 2 1 0 name osclen osclrdy osclf[3:0] oscld[1:0] type r/w r r.w r/w reset 0 0 varies varies varies varies 0 0 sfr address = 0xe3; bit name function 7 osclen internal l-f oscillator enable. 0: internal l-f oscillator disabled. 1: internal l-f oscillator enabled. 6 osclrdy internal l-f oscillator ready. 0: internal l-f oscillator frequency not stabilized. 1: internal l-f oscilla tor frequency stabilized. 5:2 osclf[3:0] internal l-f oscillator frequency control bits. fine-tune control bits for the internal l-f oscillator fr equency. when set to 0000b, the l-f oscillator oper ates at its fastest setting. when set to 1111b, the l-f oscillator operates at its slowest setting. 1:0 oscld[1:0] internal l-f oscillator divider select. 00: divide by 8 selected. 01: divide by 4 selected. 10: divide by 2 selected. 11: divide by 1 selected.
rev. 0.2 121 c8051f336/7/8/9 19.4. external oscill ator drive circuit the external oscillator circuit may drive an external cr ystal, ceramic resona tor, capacitor, or rc network. a cmos clock may also provide a clock input. for a cr ystal or ceramic resonator configuration, the crys - tal/resonator must be wired across the xtal 1 and xtal2 pins as shown in option 1 of figure 19.1 . a 10 m ? resistor also must be wired across the xtal2 an d xtal1 pins for the crystal/resonator configura - tion. in rc, capacitor, or cmos cl ock configuration, the clock source should be wired to the xtal2 pin as shown in option 2, 3, or 4 of figure 19.1 . the type of external oscillator must be selected in the oscxcn register, and the frequency control bits (xfcn) must be selected appropriately (see sfr definition 19.5 ). important note on external oscillator usage: port pins must be configured when using the external oscillator circuit. when the external oscillator drive ci rcuit is enabled in crystal/r esonator mode, port pins p0.2 and p0.3 are used as xtal1 and xtal2 respectively. when the ex ternal oscillator drive circuit is enabled in capacitor, rc, or cmos clock mode, port pin p0.3 is used as xtal2. the port i/o crossbar should be configured to skip the port pins used by the oscillator circuit; see section ?20.3. priority crossbar decoder? on page 131 for crossbar configuration. additionally, when using the ex ternal oscillator circuit in crystal/resonator, capacitor, or rc mode, the associated port pins should be configured as analog inputs . in cmos clock mode, the associated pin should be configured as a digital input . see section ?20.4. port i/o initialization? on page 133 for details on port input mode selection.
sfr definition 19.5. oscxcn: external oscillator control bit 7 6 5 4 3 2 1 0 name xtlvld xoscmd[2:0] xfcn[2:0] type r r/w r r/w reset 0 0 0 0 0 0 0 0 c8051f336/7/8/9 122 rev. 0.2 sfr address = 0xb1; bit name function 7 xtlvld crystal oscillator valid flag. (read only when xoscmd = 11x.) 0: crystal oscillator is u nused or not yet stable. 1: crystal oscillator is running and stable. 6:4 xoscmd[2:0] external oscillat or mode select. 00x: external oscillator circuit off. 010: external cmos clock mode. 011: external cmos clock mode with divide by 2 stage. 100: rc oscillator mode. 101: capacitor oscillator mode. 110: crystal oscillator mode. 111: crystal oscillator mode with divide by 2 stage. 3 unused read = 0; write = don?t care 2:0 xfcn[2:0] external oscillator frequency control bits. set according to the desired frequency for crystal or rc mode. set according to the desired k factor for c mode. xfcn crystal mode rc mode c mode 000 f 32 khz f 25 khz k factor = 0.87 001 32 khz < f 84 khz 25 khz < f 50 khz k factor = 2.6 010 84 khz < f 225 khz 50 khz < f 100 khz k factor = 7.7 011 225 khz < f 590 khz 100 khz < f 200 khz k factor = 22 100 590 khz < f 1.5 mhz 200 khz < f 400 khz k factor = 65 101 1.5 mhz < f 4 mhz 400 khz < f 800 khz k factor = 180 110 4 mhz < f 10 mhz 800 khz < f 1.6 mhz k factor = 664 111 10 mhz < f 30 mhz 1.6 mhz < f 3.2 mhz k factor = 1590
rev. 0.2 123 c8051f336/7/8/9 19.4.1. external crystal example if a crystal or ceramic resonator is used as an external oscillator source for the mcu, the circuit should be configured as shown in figure 19.1 , option 1. the external oscillato r frequency contro l value (xfcn) should be chosen from the crystal column of the table in sfr definition 19.5 (oscxcn register). for example, an 11.0592 mhz crystal requires an xfcn setting of 111b and a 32.768 khz watch crystal requires an xfcn setting of 001b. after an external 32.768 khz oscillator is stabilized, the xfcn setting can be switched to 000 to save power. it is recommended to enable the missing clock detector before switching the system clock to any external oscillator source. when the crystal oscillator is first e nabled, the oscillator amplitude detecti on circuit requires a settling time to achieve proper bias. introducing a delay of 1 ms between enabling the o scillator and checking the xtlvld bit will prevent a premature switch to the extern al oscillator as the system clock. switching to the external oscillator before the crysta l oscillator has stabilized can result in unpredictable behavior. the rec - ommended procedure is: step 1. force xtal1 and xtal2 to a low state. th is involves enabling the crossbar and writing ?0? to the port pins associated with xtal1 and xtal2. step 2. configure xtal1 and xtal2 as analog inputs using. step 3. enable the external oscillator. step 4. wait at least 1 ms. step 5. poll for xtlvld => ?1?. step 6. enable the missing clock detector. step 7. switch the system cl ock to the external oscillator. important note on external crystals: crystal oscillator circuits are qui te sensitive to pcb layout. the crystal should be placed as close as possible to the xtal pins on the device. the traces should be as short as possible and shielded with ground plane fr om any other traces which could introduce noise or interference.
c8051f336/7/8/9 124 rev. 0.2 the capacitors shown in the external crystal configur ation provide the load capacitance required by the crystal for correct oscillation. these capacitors are "in series" as seen by the crystal and "in parallel" with the stray capacitance of the xtal1 and xtal2 pins. note: the desired load capacitance depends upon the crystal and the manufacturer. please refer to the crystal data sheet when completing these calculations. for example, a tuning-fork crystal of 32.768 khz with a recommended load capacitance of 12.5 pf should use the configuration shown in figure 19.1 , option 1. the total value of th e capacitors and the stray capac - itance of the xtal pins should equal 25 pf. with a stray capacitance of 3 pf per pin, the 22 pf capacitors yield an equivalent capacitance of 12.5 pf across the crystal, as shown in figure 19.2 . xtal1 xtal2 10m ? 22pf* 22pf* 32.768 khz * capacitor values depend on crystal specifications figure 19.2. external 32.768 khz quartz crystal oscillator connection diagram
rev. 0.2 125 c8051f336/7/8/9 19.4.2. external rc example if an rc network is used as an external oscillator so urce for the mcu, the circ uit should be configured as shown in figure 19.1 , option 2. the capacitor should be no greater than 100 pf; however for very small capacitors, the total capacitance may be dominated by parasitic capacitance in the pcb layout. to deter - mine the required external oscilla tor frequency control va lue (xfcn) in the oscxcn register, first select the rc network value to produce the de sired frequency of osc illation, according to equation 1 , where f = the frequency of oscillation in mhz, c = th e capacitor value in pf, and r = the pull-up resistor value in k ? . equation 1. rc mode oscillator frequency f 1.23 10 3 rc () ? = for example: if the frequency desired is 100 khz, let r = 246 k ? and c = 50 pf: f = 1.23( 10 3 ) / rc = 1.23 ( 10 3 ) / [ 246 x 50 ] = 0.1 mhz = 100 khz referring to the table in sfr definition 19.5, the required xfcn setting is 010b. 19.4.3. external capacitor example if a capacitor is used as an external oscillator for t he mcu, the circuit should be configured as shown in figure 19.1 , option 3. the capacitor should be no greater than 100 pf; however for very small capacitors, the total capacitance may be dominated by parasiti c capacitance in the pcb layout. to determine the required external oscillato r frequency control value (xfcn) in th e oscxcn register, select the capaci - tor to be used and find the fre quency of oscillation according to equation 2 , where f = the frequency of oscillation in mhz, c = the capacitor value in pf, and v dd = the mcu power supply in volts. equation 2. c mode oscillator frequency fkf () rv dd () ? = for example: assume v dd = 3.0 v and f = 150 khz: f = kf / (c x vdd) 0.150 mhz = kf / (c x 3.0) since the frequency of roughly 150 khz is desired, sele ct the k factor from the table in sfr definition 19.5 (oscxcn) as kf = 22: 0.150 mhz = 22 / (c x 3.0) c x 3.0 = 22 / 0.150 mhz c = 146.6 / 3.0 pf = 48.8 pf therefore, the xfcn value to use in this example is 011b and c = 50 pf.
c8051f336/7/8/9 126 rev. 0.2 20. port input/output digital and analog resources are available through 17 (c8051f336/7) or 21 (c8051f338/9) i/o pins. port pins p0.0-p2.3 can be defined as general-purpose i /o (gpio), assigned to one of the internal digital resources, or assigned to an analog function as shown in figure 20.3 . port pin p2.4 on the c8051f338/9 and p2.0 on the c8051f336/7 can be used as gpio and are shared with the c2 interface data signal (c2d). the designer has complete control over which functions are assigned, limit ed only by the number of physical i/o pins. this resource assignment flexibility is achieved through the use of a pr iority crossbar decoder. note that the state of a port i/o pin can a lways be read in the corresponding port latch, regard - less of the crossbar settings. the crossbar assigns the selected internal digital reso urces to the i/o pins based on the priority decoder ( figure 20.3 and figure 20.4 ). the registers xbr0 and xbr1, defined in sfr definition 20.1 and sfr definition 20.2 , are used to select internal digital functions. all port i/os are 5 v tolerant (refer to figure 20.2 for the port cell circuit). the port i/o cells are configured as either push-pull or open-drain in the port output mode registers (pnmdout, where n = 0,1). complete electrical specifications for port i/o are given in table 6.3 on page 36 .
xbr0, xbr1, pnskip registers digital crossbar priority decoder 2 p0 i/o cells p0.0 p0.7 8 port match p0mask, p0mat p1mask, p1mat uart (internal digital signals) highest priority lowest priority sysclk 2 smbus t0, t1 2 4 pca 2 cp0 outputs spi 4 p1 i/o cells p1.0 8 (port latches) p0 (p0.0-p0.7) (p1.0-p1.7) 8 8 p1 p2 i/o cell p2 (p2.0-p2.3*) 4 4 pnmdout, pnmdin registers p1.7 p2.0 p2.3* to analog peripherals (adc0, cp0, vref, xtal) external interrupts ex0 and ex1 *p2.1-p2.3 only available on qfn24 packages rev. 0.2 127 c8051f336/7/8/9 figure 20.1. port i/o fun ctional block diagram 20.1. port i/o modes of operation port pins p0.0 - p2.3 use the port i/o cell shown in figure 20.2. each port i/o cell can be configured by software for analog i/o or digital i/o using the pnmdin registers. on rese t, all port i/o ce lls default to a high impedance state with weak pu ll-ups enabled until the crossbar is en abled (xbare = ?1?). 20.1.1. port pins configured for analog i/o any pins to be used as comparator or adc input, ex ternal oscillator input/out put, vref, or idac output should be configured for analog i/o (pnmdin.n = ?1?). when a pin is configured for analog i/o, its weak pul - lup, digital driver, a nd digital receiver are disabled. port pins configured for analog i/o will always read back a value of ?0?. configuring pins as analog i/o saves power and isolates the port pin from digital interference. port pins configured as digital inputs may still be used by analog peripherals; howe ver, this practice is not recom - mended and may result in measurement errors.
c8051f336/7/8/9 128 rev. 0.2 20.1.2. port pins configured for digital i/o any pins to be used by digital peripherals (uart, sp i, smbus, etc.), external digital event capture func - tions, or as gpio should be configured as digital i/o (pnmdin.n = ?1?). for digital i/o pins, one of two out - put modes (push-pull or open-drain) must be selected using the pnmdout registers. push-pull outputs (pnmdout.n = ?1?) drive the port pad to the vdd/dc+ or gnd supply rails based on the output logic value of the port pin. open-drain output s have the high side driver disabled; therefore, they only drive the port pad to gnd when the output logic value is ?0? and become high impedance inputs (both high low drivers turned off) when the output logic value is ?1?. when a digital i/o cell is placed in the high impedance st ate, a weak pull-up transistor pulls the port pad to the vdd supply voltage to ensure th e digital input is at a defined logic state. weak pull-ups are disabled when the i/o cell is driven to gnd to minimize power consumption and may be globally disabled by setting weakpud to ?1?. the user should ensure that digital i/o are alwa ys internally or externally pu lled or driven to a valid logic state to minimize power consumption. port pins configured for digital i/o always read back the logic state of the port pad, regardless of the output logic value of the port pin. gnd vdd vdd (weak) port pad to/from analog peripheral pxmdin.x (1 for digital) (0 for analog) px.x ? output logic value (port latch or crossbar) xbare (crossbar enable) px.x ? input logic value (reads 0 when pin is configured as an analog i/o) pxmdout.x (1 for push-pull) (0 for open-drain) weakpud (weak pull-up disable) figure 20.2. port i/o cell block diagram 20.1.3. interfacing port i/o to 5v logic all port i/o configured for digital, open-drain operation are capable of interfacing to digital logic operating at a supply voltage higher than vdd and less than 5.25v. an external pull-up resistor to the higher supply voltage is typically required for most systems. important note: in a multi-voltage interface, the external pull-up resistor should be sized to allow a current of at least 150ua to flow into the port pin when t he supply voltage is between (vdd + 0.6v) and (vdd + 1.0v). once the port pin voltage increases beyond this range, the current flowing into the port pin is minimal.
rev. 0.2 129 c8051f336/7/8/9 20.2. assigning port i/o pins to analog and digital functions port i/o pins p0.0 - p2.3 can be assigned to various ana log, digital, and external interrupt functions. the port pins assigned to analog functions should be c onfigured for analog i/o, and port pins assigned to digital or external interrupt functions should be configured for digital i/o. 20.2.1. assigning port i/o pins to analog functions ta b l e 20.1 shows all available analog functi ons that require port i/o assignments. port pins selected for these analog functions should have their corresponding bit in pnskip set to ?1?. this reserves the pin for use by the analog func tion and does not allow it to be claimed by the crossbar. table 20.1 shows the potential mapping of port i/o to each analog function. table 20.1. port i/o assignmen t for analog functions analog function potentially assignable port pins sfr(s) used for assignment adc input p0.0 - p2.3 amx0p, amx0n, pnskip comparator0 input p0.0 - p2.3 cpt0mx, pnskip voltage reference (vref0) p0.0 ref0cn, pnskip current dac output (ida0) p0.1 ida0cn, pnskip external oscillator in crystal mode (xtal1) p0.2 oscxcn, pnskip external oscillator in rc, c, or crystal mode (xtal2) p0.3 oscxcn, pnskip
c8051f336/7/8/9 130 rev. 0.2 20.2.2. assigning port i/o pins to digital functions any port pins not assigned to analog functions may be assigned to digital functi ons or used as gpio. most digital functions rely on the crossbar for pin assi gnment; however, some digital functions bypass the crossbar in a manner similar to the analog functi ons listed above. port pins used by these digital functions and any port pins selected for use as gpio should have their corresponding bit in pnskip set to ?1?. ta b l e 20.2 shows all available digital functions and the potential mapping of port i/o to each digital function. table 20.2. port i/o assignment for digital functions digital function potentially assignable port pins sfr(s) used for assignment uart0, spi0, smbus, cp0, cp0a, sysclk, pca0 (cex0-2 and eci), t0 or t1. any port pin available for assignment by the crossbar. this includes p0.0 - p2.3 pins which have their pnskip bit set to ?0?. note: the crossbar will always assign uart0 pins to p0.4 and p0.5. xbr0, xbr1 any pin used for gpio p0.0 - p2.4 p0skip, p1skip, p2skip 20.2.3. assigning port i/o pins to external digital event capture functions external digital event captur e functions can be used to trigger an interrupt or wake the device from a low power mode when a transition occurs on a digital i/o pin. the digital event capture functions do not require dedicated pins and will function on both gpio pins (pnskip = ?1?) and pins in use by the crossbar (pnskip = ?0?). external digital event capture functions cannot be used on pins configured for analog i/o. ta b l e 20.3 shows all available external digital event capture functions. table 20.3. port i/o assignment for external digital event capture functions digital function potentially assignable port pins sfr(s) used for assignment external interrupt 0 p0.0 - p0.7 it01cf external interrupt 1 p0.0 - p0.7 it01cf port match p0.0 - p1.7 p0mask, p0mat p1mask, p1mat
rev. 0.2 131 c8051f336/7/8/9 20.3. priority crossbar decoder the priority crossb ar decoder (figure 20.3) assigns a priority to each i/o function, starting at the top with uart0. when a digital resource is selected, the leas t-significant unassigned port pin is assigned to that resource (excluding uart0, which is a lways at pins 4 and 5). if a port pin is assigned, the crossbar skips that pin when assigning the next se lected resource. additionally, the crossbar will skip port pins whose associated bits in the pnskip registers are set. the pn skip registers allow software to skip port pins that are to be used for analog input, dedicated functions, or gpio. important note on crossbar configuration: if a port pin is claimed by a peripheral without use of the crossbar, its corresponding pnskip bit should be set. this applies to p0.0 if vref is used, p0.3 and/or p0.2 if the external oscillat or circuit is enabled, p0.6 if the adc or idac is configured to use the external conversion start signal (cnvstr), and any selected adc or comparator inputs. the crossbar skips selected pins as if they were already a ssigned, and moves to the next unassigned pin. figure 20.3 shows the crossbar decoder priority with no port pins skipped (p0skip, p1skip = 0x00); figure 20.4 shows the crossbar decoder priority with the xtal1 (p0. 2) and xtal2 (p0.3) pins skipped (p0skip = 0x0c). v re f ida x1 x2 cnvstr 01234567012345670 1 2 2 2 3 2 4 2 sysclk cex0 cex1 cex2 eci 00000000000000000000 notes: 1. nss is only pinned out in 4-wire spi mode 2. pins p2.1-p2.4 only on qfn24 package p1 nss 1 sck miso mosi rx0 sf signals pin i/o special function signals are not assigned by the crossbar. when these signals are enabled, the crossbar must be manually configured to skip their corresponding port pins. port pin potentially available to peripheral sf signals t1 p0skip[0:7] p1skip[0:7] p2skip[0:3] p2 pin not available for crossbar peripherals. cp0a t0 tx0 cp0 sda scl p0 figure 20.3. crossbar priority decoder with no pins skipped
v ref ida x1 x2 cnvstr 01234567012345670 1 2 2 2 sysclk cex0 cex1 cex2 eci 0011000000000000000 notes: 1. nss is only pinned out in 4-wire spi mod e 2. pins p2.1-p2.4 only on qfn24 package t0 p1skip[0:7] special function signals are not assigned by the crossbar. w hen these signals are enabled, the crossbar must be manually configured to skip their corresponding port pins. port pin potentially available to peripheral sf signals t1 p0skip[0:7] cp0 sda scl cp0a rx0 sf signals pin i/o tx0 nss 1 sck miso mosi p2 p2skip[0: 3 p0 p1 c8051f336/7/8/9 132 rev. 0.2 figure 20.4. crossbar priority d ecoder with crystal pins skipped registers xbr0 and xbr1 are used to assign the digital i/o resources to the physical i/o port pins. note that when the smbus is selected, the crossbar assi gns both pins associated with the smbus (sda and scl); when the uart is selected, the crossbar assign s both pins associated with the uart (tx and rx). uart0 pin assignments are fixed for bootloading purp oses: uart tx0 is always assigned to p0.4; uart rx0 is always assigned to p0.5. standard port i/os appear contiguously after the prioritized functions have been assigned. important note: the spi can be operated in either 3-wire or 4-wire modes, pending the state of the nssmd1?nssmd0 bits in register spi0cn. according to the spi mode, the nss signal may or may not be routed to a port pin.
rev. 0.2 133 c8051f336/7/8/9 20.4. port i/o initialization port i/o initialization cons ists of the following steps: step 1. select the input mode (analog or digital) for all port pins, using the port input mode register (pnmdin). step 2. select the output mode (open-drain or push -pull) for all port pins, using the port output mode register (pnmdout). step 3. select any pins to be skipped by the i/o crossbar using the port skip registers (pnskip). step 4. assign port pins to desired peripherals. step 5. enable the cr ossbar (xbare = ?1?). all port pins must be configured as either analog or digital inputs. any pins to be used as comparator or adc inputs should be configured as an analog inputs. when a pin is configured as an analog input, its weak pullup, digital driver, and digital receiver are disabled. this process save s power and reduces noise on the analog input. pins configured as digital inputs may still be used by analog peripherals; however this practice is not recommended. additionally, all analog input pins should be configur ed to be skipped by the crossbar (accomplished by setting the associated bits in pnskip). port input mode is set in the pnmdin register, where a ?1? indicates a digital input, and a ?0? indicates an analog input. all pins default to digital inputs on reset. see sfr defini - tion 20.8 for the pnmdin register details. the output driver characteristics of the i/o pins ar e defined using the port output mode registers (pnmd - out). each port output driver can be configured as either open drain or push- pull. this selection is required even for the digital resources selected in the xbrn registers, and is not automatic. the only exception to this is the smbus (sda, scl) pins, which are configured as open-drain regardless of the pnmdout settings. when the weakpud bi t in xbr1 is ?0?, a weak pullup is enabled for a ll port i/o con - figured as open-drain. w eakpud does not affect the push-pull port i/o. furthermo re, the weak pullup is turned off on an output that is driving a ?0? to avoid unnecessary power dissipation. registers xbr0 and xbr1 must be loaded with the approp riate values to select the digital i/o functions required by the design. setting the xbare bit in xbr1 to ?1? enables the cross bar. until the crossbar is enabled, the external pins remain as standard port i/o (in input mode), regardless of the xbrn register settings. for given xbrn register settings, one can de termine the i/o pin-out us ing the priority decode table; as an alternative, the confi guration wizard utility of the silicon labs ide software will determine the port i/o pin-assignments based on the xbrn register settings. the crossbar must be enabled to us e port pins as standard port i/o in output mode. port output drivers are disabled while the crossbar is disabled.
sfr definition 20.1. xbr0: port i/o crossbar register 0 bit 7 6 5 4 3 2 1 0 name cp0ae cp0e syscke smb0e spi0e urt0e type r r r/w r/w r/w r/w r/w r/w reset c8051f336/7/8/9 134 rev. 0.2 sfr address = 0xe1 bit name function 7:6 unused unused. read = 00b; write = don?t care. 5 cp0ae comparator0 asynchronous output enable. 0: asynchronous cp0 unavailable at port pin. 1: asynchronous cp0 routed to port pin. 4 cp0e comparator0 output enable. 0: cp0 unavailable at port pin. 1: cp0 routed to port pin. 3 syscke /sysclk output enable. 0: /sysclk unavailable at port pin. 1: /sysclk output routed to port pin. 2 smb0e smbus i/o enable. 0: smbus i/o unavailable at port pins. 1: smbus i/o routed to port pins. 1 spi0e spi i/o enable. 0: spi i/o unavailable at port pins. 1: spi i/o routed to port pins. note that the spi can be assigned either 3 or 4 gpio pins. 0 urt0e uart i/o output enable. 0: uart i/o unavailable at port pin. 1: uart tx0, rx0 routed to port pins p0.4 and p0.5. 00000000
sfr definition 20.2. xbr1: port i/o crossbar register 1 bit 7 6 5 4 3 2 1 0 name weakpud xbare t1e t0e ecie pca0me[1:0] type r/w r/w r/w r/w r/w r r/w r/w reset rev. 0.2 135 c8051f336/7/8/9 sfr address = 0xe2 bit name function 7 weakpud port i/o weak pullup disable. 0: weak pullups enabled (except for ports whose i/o are configured for analog mode). 1: weak pullups disabled. 6 xbare crossbar enable. 0: crossbar disabled. 1: crossbar enabled. 5 t1e t1 enable. 0: t1 unavailable at port pin. 1: t1 routed to port pin. 4 t0e t0 enable. 0: t0 unavailable at port pin. 1: t0 routed to port pin. 3 ecie pca0 external counter input enable. 0: eci unavailable at port pin. 1: eci routed to port pin. 2 unused unused. read = 0b; write = don?t care. 1:0 pca0me[1:0] pca module i/o enable bits. 00: all pca i/o unavailable at port pins. 01: cex0 routed to port pin. 10: cex0, cex1 routed to port pins. 11: cex0, cex1, cex2 routed to port pins. 0 0000000
c8051f336/7/8/9 136 rev. 0.2 20.5. port match port match functionality allows system events to be triggered by a logic value change on p0 or p1. a software controlled value stor ed in the pnmatch registers specifies t he expected or normal logic values of p0 and p1. a port mismatch event occurs if the logic levels of the port?s input pins no longer match the software controlled value. this allows software to be notified if a certain change or pattern occurs on p0 or p1 input pins regardless of the xbrn settings. the pnmask registers can be used to individually select which p0 a nd p1 pins should be compared against the pnmatch registers. a port mismatch event is generated if (p0 & p0mask) does not equal (p0match & p0mask) or if (p1 & p1mask) does no t equal (p1match & p1mask). a port mismatch event may be used to generate an interrupt or wake the device from a low power mode, such as idle or suspend. see the interrupts and power options chapte rs for more details on interrupt and wake-up sources. sfr definition 20.3. p0mask: port 0 mask register bit 7 6 5 4 3 2 1 0 name p0mask[7:0] type reset sfr address = 0xfe bit name function 7:0 p0mask[7:0] port 0 mask value. selects p0 pins to be compared to the corresponding bits in p0mat. 0: p0.n pin logic value is ignored an d cannot cause a port mismatch event. 1: p0.n pin logic value is compared to p0mat.n. sfr definition 20.4. p0mat: port 0 match register bit 7 6 5 4 3 2 1 0 name p0mat[7:0] type reset sfr address = 0xfd bit name function 7:0 p0mat[7:0] port 0 match value. match comparison value used on port 0 for bits in p0mat which are set to ?1?. 0: p0.n pin logic value is compared with logic low. 1: p0.n pin logic value is compared with logic high. r/w 11111111 r/w 00000000
sfr definition 20.5. p1mask: port 1 mask register bit 7 6 5 4 3 2 1 0 name p1mask[7:0] type reset rev. 0.2 137 c8051f336/7/8/9 sfr address = 0xee bit name function 7:0 p1mask[7:0] port 1 mask value. selects p1 pins to be compared to the corresponding bits in p1mat. 0: p1.n pin logic value is ignored an d cannot cause a port mismatch event. 1: p1.n pin logic value is compared to p1mat.n. sfr definition 20.6. p1mat: port 1 match register bit 7 6 5 4 3 2 1 0 name p1mat[7:0] type reset sfr address = 0xed bit name function 7:0 p1mat[7:0] port 1 match value. match comparison value used on port 1 for bits in p1mat which are set to ?1?. 0: p1.n pin logic value is compared with logic low. 1: p1.n pin logic value is compared with logic high. r/w 11111111 r/w 00000000
c8051f336/7/8/9 138 rev. 0.2 20.6. special function registers for accessing and configuring port i/o all port i/o are accessed through corresponding specia l function registers (sfrs) that are both byte addressable and bit addressable. when writing to a port, the value written to the sfr is latched to maintain the output data value at each pin. when re ading, the logic levels of the port's input pins are returned regardless of the xbrn settings (i.e., even when the pin is assigned to another signal by the crossbar, the port register can always read its corres ponding port i/o pin). the exception to this is the execution of the read-modify-write instructions that ta rget a port latch register as the destination. the read-modify-write instructions when operating on a port sfr are the following: anl, orl, xrl, jbc, cpl, inc, dec, djnz and mov, clr or setb, when the de stination is an individual bit in a port sfr. for these instructions, the value of the latch register (not the pin) is read, modified, and written back to the sfr. each port has a corresponding pnskip register which a llows its individual port pins to be assigned to digital functions or skipped by the crossbar. all port pins used for analog functions, gpio, or dedicated digital functions such as the emif sh ould have their pnskip bit set to ?1?. the port input mode of the i/o pins is defined usi ng the port input mode registers (pnmdin). each port cell can be configured for analog or digital i/o. this selection is required even for the digital resources selected in the xbrn registers, and is not automatic. th e only exception to this is p2.4, which can only be used for digital i/o. the output driver characteristics of the i/o pins ar e defined using the port output mode registers (pnmd - out). each port output driver can be configured as either open drain or push- pull. this selection is required even for the digital resources selected in the xbrn registers, and is not automatic. the only exception to this is the smbus (sda, scl) pins, which are configured as open-drain regardless of the pnmdout settings. sfr definition 20.7. p0: port 0 bit 7 6 5 4 3 2 1 0 name p0[7:0] type reset sfr address = 0x80 bit name description write read 7:0 p0[7:0] port 0 data. sets the port latch logic value or reads the port pin logic state in port cells con - figured for digital i/o. 0: set output latch to logic low. 1: set output latch to logic high. 0: p0.n port pin is logic low. 1: p0.n port pin is logic high. r/w 11111111
sfr definition 20.8. p0mdin: port 0 input mode bit 7 6 5 4 3 2 1 0 name p0mdin[7:0] type reset rev. 0.2 139 c8051f336/7/8/9 sfr address = 0xf1 bit name function 7:0 p0mdin[7:0] analog configuration bits for p0.7?p0.0 (respectively). port pins configured for analog mode ha ve their weak pullup, digital driver, and digital receiver disabled. 0: corresponding p0.n pin is configured for analog mode. 1: corresponding p0.n pin is not configured for analog mode. sfr definition 20.9. p0mdout: port 0 output mode bit 7 6 5 4 3 2 1 0 name p0mdout[7:0] type reset sfr address = 0xa4 bit name function 7:0 p0mdout[7:0] output configuration bits for p0.7?p0.0 (respectively). these bits are ignored if the correspondi ng bit in register p0mdin is logic 0. 0: corresponding p0.n output is open-drain. 1: corresponding p0.n output is push-pull. r/w 11111111 r/w 00000000
sfr definition 20.10. p0skip: port 0 skip bit 7 6 5 4 3 2 1 0 name p0skip[7:0] type reset c8051f336/7/8/9 140 rev. 0.2 sfr address = 0xd4 bit name function 7:0 p0skip[7:0] port 0 crossbar skip enable bits. these bits select port 0 pins to be skip ped by the crossbar decoder. port pins used for analog, special functions or gpio should be skipped by the crossbar. 0: corresponding p0.n pin is not skipped by the crossbar. 1: corresponding p0.n pin is skipped by the crossbar. sfr definition 20.11. p1: port 1 bit 7 6 5 4 3 2 1 0 name p1[7:0] type reset sfr address = 0x90 bit name description write read 7:0 p1[7:0] port 1 data. sets the port latch logic value or reads the port pin logic state in port cells con - figured for digital i/o. 0: set output latch to logic low. 1: set output latch to logic high. 0: p1.n port pin is logic low. 1: p1.n port pin is logic high. r/w 00000000 r/w 11111111
sfr definition 20.12. p1mdin: port 1 input mode bit 7 6 5 4 3 2 1 0 name p1mdin[7:0] type reset rev. 0.2 141 c8051f336/7/8/9 sfr address = 0xf2 bit name function 7:0 p1mdin[7:0] analog configuration bits for p1.7?p1.0 (respectively). port pins configured for analog mode ha ve their weak pullup, digital driver, and digital receiver disabled. 0: corresponding p1.n pin is configured for analog mode. 1: corresponding p1.n pin is not configured for analog mode. sfr definition 20.13. p1mdout: port 1 output mode bit 7 6 5 4 3 2 1 0 name p1mdout[7:0] type reset sfr address = 0xa5 bit name function 7:0 p1mdout[7:0] output configuration bits for p1.7?p1.0 (respectively). these bits are ignored if the correspondi ng bit in register p1mdin is logic 0. 0: corresponding p1.n output is open-drain. 1: corresponding p1.n output is push-pull. r/w 11111111 r/w 00000000
sfr definition 20.14. p1skip: port 1 skip bit 7 6 5 4 3 2 1 0 name p1skip[7:0] type reset c8051f336/7/8/9 142 rev. 0.2 sfr address = 0xd5 bit name function 7:0 p1skip[7:0] port 1 crossbar skip enable bits. these bits select port 1 pins to be skip ped by the crossbar decoder. port pins used for analog, special functions or gpio should be skipped by the crossbar. 0: corresponding p1.n pin is not skipped by the crossbar. 1: corresponding p1.n pin is skipped by the crossbar. sfr definition 20.15. p2: port 2 bit 7 6 5 4 3 2 1 0 name p2[4:0] type reset sfr address = 0xa0 bit name description write read 7:5 unused unused. don?t care 000b 4:0 p2[4:0] port 2 data. sets the port latch logic value or reads the port pin logic state in port cells con - figured for digital i/o. 0: set output latch to logic low. 1: set output latch to logic high. 0: p2.n port pin is logic low. 1: p2.n port pin is logic high. note: pins p2.1-p2.4 are only available in qfn24-packaged devices. r/w 00000000 rrr r/w 00011111
sfr definition 20.16. p2mdin: port 2 input mode bit 7 6 5 4 3 2 1 0 name p2mdin[7:0] type reset rev. 0.2 143 c8051f336/7/8/9 sfr address = 0xf3 bit name function 7:4 unused unused. read = 0000b; write = don?t care 3:0 p2mdin[3:0] analog configuration bits for p2.3?p2.0 (respectively). port pins configured for analog mode ha ve their weak pullup, digital driver, and digital receiver disabled. 0: corresponding p2.n pin is configured for analog mode. 1: corresponding p2.n pin is not configured for analog mode. note: pins p2.1-p2.4 are only available in qfn24-packaged devices. sfr definition 20.17. p2mdout: port 2 output mode bit 7 6 5 4 3 2 1 0 name p2mdout[4:0] type reset sfr address = 0xa6 bit name function 7:5 unused unused. read = 000b; write = don?t care 4:0 p2mdout[4:0] output configuration bits for p2.4?p2.0 (respectively). these bits are ignored if the correspondi ng bit in register p2mdin is logic 0. 0: corresponding p2.n output is open-drain. 1: corresponding p2.n output is push-pull. note: pins p2.1-p2.4 are only available in qfn24-packaged devices. rrrr r/w 00001111 rrr r/w 00000000
sfr definition 20.18. p2skip: port 2 skip bit 7 6 5 4 3 2 1 0 name p2skip[7:0] type reset c8051f336/7/8/9 144 rev. 0.2 sfr address = 0xd6 bit name function 7:4 unused unused. read = 0000b; write = don?t care 3:0 p2skip[3:0] port 2 crossbar skip enable bits. these bits select port 2 pins to be skip ped by the crossbar decoder. port pins used for analog, special functions or gpio should be skipped by the crossbar. 0: corresponding p2.n pin is not skipped by the crossbar. 1: corresponding p2.n pin is skipped by the crossbar. note: pins p2.1-p2.4 are only available in qfn24-packaged devices. rrrr r/w 00000000
rev. 0.2 145 c8051f336/7/8/9 21. smbus the smbus i/o interface is a two-wire, bi-directional serial bus. the smbus is compliant with the system management bus specification, version 1.1, and compatible with the i2c serial bus. reads and writes to the interface by the system contro ller are byte oriented with the smbu s interface autonom ously controlling the serial transfer of the data. data can be transferre d at up to 1/20th of the system clock as a master or slave (this can be faster than allowed by the smbus specification, depending on the system clock used). a method of extending the clock-low duration is ava ilable to accommodate devices with different speed capabilities on the same bus. the smbus interface may operate as a master and/or slave, and may function on a bus with multiple mas - ters. the smbus provides control of sda (serial data), scl (serial clock) generation and synchronization, arbitration logic, and start/stop control and genera tion. the smbus peripheral can be fully driven by software (i.e. software accepts/re jects slave addresses, and generate s acks), or hardware slave address recognition and automatic ack gener ation can be enabled to minimize software overhead. a block dia - gram of the smbus peripheral and the associated sfrs is shown in figure 21.1 . data path control smbus control logic c r o s s b a r scl filter n sda control scl control interrupt request port i/o smb0cn s t a a c k r q a r b l o s t a c k s i t x m o d e m a s t e r s t o 01 00 10 11 t0 overflow t1 overflow tmr2h overflow tmr2l overflow smb0cf e n s m b i n h b u s y e x t h o l d s m b t o e s m b f t e s m b c s 1 s m b c s 0 0 1 2 3 4 5 6 7 smb0dat sda filter n smb0adr s l v 4 s l v 2 s l v 1 s l v 0 g c s l v 5 s l v 6 s l v 3 smb0adm s l v m 4 s l v m 2 s l v m 1 s l v m 0 e h a c k s l v m 5 s l v m 6 s l v m 3 arbitration scl synchronization hardware ack generation scl generation (master mode) sda control hardware slave address recognition irq generation figure 21.1. smbus block diagram 21.1. supporting documents it is assumed the reader is fam iliar with or has access to th e following supporting documents:
c8051f336/7/8/9 146 rev. 0.2 1. the i2c-bus and how to use it (including specifications), philips semiconductor. 2. the i2c-bus specification?vers ion 2.0, philips semiconductor. 3. system management bus specification? version 1.1, sbs implementers forum. 21.2. smbus configuration figure 21.2 shows a typical smbus configuration. the sm bus specification allows any recessive voltage between 3.0 v and 5.0 v; different devices on the bus may operate at different voltage levels. the bi-direc - tional scl (serial clock) and sda (serial data) lines mu st be connected to a positive power supply voltage through a pullup resistor or similar circuit. every devi ce connected to the bus must have an open-drain or open-collector output for both the scl and sda lines, so that both are pulled high (recessive state) when the bus is free. the maximum number of devices on the bus is limited only by the requirement that the rise and fall times on the bus not exceed 300 ns and 1000 ns, respectively. vdd = 5v master device slave device 1 slave device 2 vdd = 3v vdd = 5v vdd = 3v sda scl figure 21.2. typical smbus configuration 21.3. smbus operation two types of data transfers are possible: data transfers from a master transmitter to an addressed slave receiver (write), and data transfers from an addres sed slave transmitter to a master receiver (read). the master device initiates both types of data transfer s and provides the serial clock pulses on scl. the smbus interface may operate as a master or a slave, and multiple master devices on the same bus are supported. if two or more masters attempt to initiate a data transfer simultaneously, an arbitration scheme is employed with a single master always winning the arbitr ation. note that it is not necessary to specify one device as the master in a system ; any device who transmits a star t and a slave address becomes the master for the duration of that transfer. a typical smbus transaction consists of a start cond ition followed by an address byte (bits7?1: 7-bit slave address; bit0: r/w direction bit), one or more bytes of data, and a stop condition. bytes that are received (by a master or slave) are acknowledg ed (ack) with a low sda during a high scl (see figure 21.3 ). if the receiving device does not ack, the transmitting devi ce will read a nack (not acknowl - edge), which is a high sda during a high scl. the direction bit (r/w) occupies the least-significant bit position of the address byte. the direction bit is set to logic 1 to indicate a "read" operation and cleared to logic 0 to indicate a "write" operation. all transactions are initiated by a master, with one or more addressed slave devices as the target. the master generates the start condition and then transmit s the slave address and direction bit. if the trans -
rev. 0.2 147 c8051f336/7/8/9 action is a write operation from the master to the slave, the master tr ansmits the data a byte at a time waiting for an ack from the slave at the end of each byte. for read operations , the slave transmits the data waiting for an ack from the master at the end of each byte. at the end of the data transfer, the master generates a stop condition to terminate the transaction and free the bus. figure 21.3 illustrates a typical smbus transaction. sla6 sda sla5-0 r/w d7 d6-0 scl slave address + r/w data byte start ack nack stop figure 21.3. smbus transaction 21.3.1. transmitter vs. receiver on the smbus communications interface, a device is the ?transmitter? when it is sending an address or data byte to another device on the bus. a device is a ?receiver? when an ad dress or data byte is being sent to it from another device on the bus. the transmitter controls the sda line during the address or data byte. after each byte of address or data information is sent by the transmitter, the receiver sends an ack or nack bit during the ack phase of the transfer, dur ing which time the receiver controls the sda line. 21.3.2. arbitration a master may start a transfer only if the bus is free. th e bus is free after a stop condition or after the scl and sda lines remain high for a specified time (see section ?21.3.5. scl high (smbus free) timeout? on page 148 ). in the event that two or more devices attempt to begin a transfer at the same time, an arbitra - tion scheme is employed to force one master to give up the bus. the master devices continue transmitting until one attempts a high while the other transmits a low. since the bus is open-drain, the bus will be pulled low. the master attempting th e high will detect a low sda and lo se the arbitration. the winning master continues its transmission without interruption; the losing master becomes a slave and receives the rest of the transfer if addressed. this arbitration scheme is non-destru ctive: one device always wins, and no data is lost.
c8051f336/7/8/9 148 rev. 0.2 21.3.3. clock low extension smbus provides a clock synchronizati on mechanism, similar to i2c, wh ich allows devices with different speed capabilities to coexist on the bus. a clock-low extension is used du ring a transfer in order to allow slower slave devices to communica te with faster masters. the slave may temporarily hold the scl line low to extend the clock low period, effectively decreasing the serial clock frequency. 21.3.4. scl low timeout if the scl line is held low by a slave device on the bus , no further communication is possible. furthermore, the master cannot force the scl line high to correct th e error condition. to solve this problem, the smbus protocol specifies that devices participating in a tran sfer must detect any clock cy cle held low longer than 25 ms as a ?timeout? condition. devices that have det ected the timeout condition must reset the communi - cation no later than 10 ms after detecting the timeout condition. when the smbtoe bit in smb0cf is set, timer 3 is used to detect scl low timeouts. timer 3 is forced to reload when scl is high, and allowed to count when scl is low. with timer 3 enabled and configured to overflow after 25 ms (and smbtoe set), the timer 3 interrupt service routine can be used to reset (disable and re-enable) the smbus in the event of an scl low timeout. 21.3.5. scl high (smbus free) timeout the smbus specification stipulates that if the scl and sda lines remain high for more that 50 s, the bus is designated as free. when the sm bfte bit in smb0cf is set, the bu s will be considered free if scl and sda remain high for more than 10 smbus clock source periods (as defined by the timer configured for the smbus clock source). if the smbus is waiting to generate a master start, the start will be generated following this timeout. note that a clock source is required for free timeout detection, even in a slave-only implementation. 21.4. using the smbus the smbus can operate in both master and slave modes. the interface provides timing and shifting con - trol for serial transfers; higher level protocol is dete rmined by user software. the smbus interface provides the following application-independent features: ? byte-wise serial data transfers ? clock signal generation on scl (master mode only) and sda data synchronization ? timeout/bus error recognition, as define d by the smb0cf configuration register ? start/stop timing, detection, and generation ? bus arbitration ? interrupt generation ? status information ? optional hardware recognition of slave address and automatic acknowledgement of address/data smbus interrupts are generated for each data byte or slave address that is transferred. when hardware acknowledgement is disabled, the point at which the interrupt is generated depends on whether the hard - ware is acting as a data transmitter or receiver. when a transmitter (i.e. sending address/data, receiving an ack), this interrupt is generated after the ack cycle so that software may read the received ack value; when receiving data (i.e. receiving address/data, sending an ack), this interrupt is generated before the ack cycle so that software may def ine the outgoing ack value. if har dware acknowledgement is enabled, these interrupts are always generated after the ack cycle. see section 21.5 for more details on transmis - sion sequences.
rev. 0.2 149 c8051f336/7/8/9 interrupts are also generated to indicate the beginning of a transfer when a master (start generated), or the end of a transfer when a slave (stop detected) . software should read the smb0cn (smbus control register) to find the cause of the smbus inte rrupt. the smb0cn register is described in section 21.4.2 ; ta b l e 21.5 provides a quick smb0cn decoding reference. 21.4.1. smbus configuration register the smbus configuration register (s mb0cf) is used to enable the smbus master and/or slave modes, select the smbus clock source, and select the smbus timing and timeout options . when the ensmb bit is set, the smbus is enabled for all master and slave events. slave events may be disabled by setting the inh bit. with slave events inhibited, the smbus in terface will still monitor the scl and sda pins; however, the interface will nack all received addresses and will not generate any slave inte rrupts. when the inh bit is set, all slave events will be inhibited following the ne xt start (interrupts will cont inue for the duration of the current transfer). table 21.1. smbus clock source selection the smbcs1?0 bits select the smbus clock source, which is used only when operating as a master or when the free timeout detection is enabled. when op erating as a master, overflows from the selected source determine the absolute minimum scl low and high times as defined in equation 21.1 . note that the selected clock source may be shared by other peripherals so long as the timer is left running at all times. for example, timer 1 overflows may generate the smbus and uart baud rates simultaneously. timer configuration is covered in section ?24. timers? on page 187 . t highmin t lowmin 1 f clocksourceoverflow ---------------- ------------------ ----------- - == equation 21.1. minimum scl high and low times the selected clock source should be configured to establish the minimum scl high and low times as per equation 21.1 . when the interface is operating as a master (and scl is not driven or extended by any other devices on the bus), the typica l smbus bit rate is approximated by equation 21.2 . bitrate f clocksourceoverflow 3 --------------- ----------------- ------------- - = equation 21.2. typical smbus bit rate smbcs1 smbcs0 smbus clock source 0 0 timer 0 overflow 0 1 timer 1 overflow 1 0 timer 2 high byte overflow 1 1 timer 2 low byte overflow
c8051f336/7/8/9 150 rev. 0.2 figure 21.4 shows the typical scl generation described by equation 21.2. notice that t high is typically twice as large as t low . the actual scl output may vary due to other devices on the bus (scl may be extended low by slower slave devices, or driven low by contending master devices). the bit rate when operating as a master will never exce ed the limits defined by equation equation 21.1 . scl timer source overflows scl high timeout t low t high figure 21.4. typical smbus scl generation setting the exthold bit extends the minimum setup and hold times for the sda line. the minimum sda setup time defines the absolute mini mum time that sda is stable before scl transitions from low-to-high. the minimum sda hold time defines the absolute minimum time that the current sda value remains stable after scl transitions from high-to-low. exthold should be set so that the minimum setup and hold times meet the smbus specification requirements of 250 ns and 300 ns, respectively. ta b l e 21.2 shows the min - imum setup and hold times for the two exthold settings. setup and hold time extensions are typically necessary when sysclk is above 10 mhz. table 21.2. minimum sda setup and hold times *note: setup time for ack bit transmissions and the msb of all data transfers. when using software acknowledgement, the s/w delay occurs between the time smb0dat or ack is written and when si is cleared. note that if si is cleared in the same write that defines the outgoing ack value, s/w delay is zero. with the smbtoe bit set, timer 3 should be configured to overflow after 25 ms in order to detect scl low timeouts (see section ?21.3.4. scl low timeout? on page 148 ). the smbus interface will force timer 3 to reload while scl is high, and allow timer 3 to count when scl is low. the timer 3 interrupt service routine should be used to reset smbus communication by disabling and re-enabling the smbus. smbus free timeout detection can be enabled by setting the smbfte bit. when this bit is set, the bus will be considered free if sda and scl remain high for more than 10 smbus clock source periods (see figure 21.4 ). exthold minimum sda setup time minimum sda hold time 0 t low ? 4 system clocks or 1 system clock + s/w delay * 3 system clocks 1 11 system clocks 12 system clocks
sfr definition 21.1. smb0cf: smbus clock/configuration bit 7 6 5 4 3 2 1 0 name ensmb inh busy exthold smbtoe smbfte smbcs[1:0] type r/w r/w r r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 rev. 0.2 151 c8051f336/7/8/9 sfr address = 0xc1 bit name function 7 ensmb smbus enable. this bit enables the smbus interface when set to ?1?. when enabled, the interface constantly monitors the sda and scl pins. 6 inh smbus slave inhibit. when this bit is set to logic 1, the smbu s does not generate an interrupt when slave events occur. this effectively removes th e smbus slave from the bus. master mode interrupts are not affected. 5 busy smbus busy indicator. this bit is set to logic 1 by hardware when a transfer is in progress. it is cleared to logic 0 when a stop or free-timeout is sensed. 4 exthold smbus setup and hold time extension enable. this bit controls the sda setup and hold times according to table 21.2. 0: sda extended setup and hold times disabled. 1: sda extended setup and hold times enabled. 3 smbtoe smbus scl timeout detection enable. this bit enables scl low timeout detection. if set to logic 1, the smbus forces timer 3 to reload while scl is high and allows timer 3 to count when scl goes low. if timer 3 is configured to split mode, only the high byte of the timer is held in reload while scl is high. timer 3 should be programmed to generate interrupts at 25 ms, and the timer 3 interrupt service routine should reset smbus communication. 2 smbfte smbus free timeout detection enable. when this bit is set to logic 1, the bus will be considered free if scl and sda remain high for more than 10 smbus clock source periods. 1:0 smbcs[1:0] smbus clock source selection. these two bits select the smbus clock sour ce, which is used to generate the smbus bit rate. the selected device should be configured according to equation 21.1 . 00: timer 0 overflow 01: timer 1 overflow 10 :timer 2 high byte overflow 11: timer 2 low byte overflow
c8051f336/7/8/9 152 rev. 0.2 21.4.2. smb0cn control register smb0cn is used to control the interface and to provid e status information (see sfr definition 21.2). the higher four bits of smb0cn (master, txmode, sta, and sto) form a status vector that can be used to jump to service routines. master indicates whether a device is the master or slave during the current transfer. txmode indicates whether the device is tr ansmitting or receiving data for the current byte. sta and sto indicate that a start and/or stop ha s been detected or generated since the last smbus interrupt. sta and sto are also used to generate start and stop conditions when operating as a mas - ter. writing a ?1? to sta will cause the smbus interfac e to enter master mode and generate a start when the bus becomes free (sta is not cleared by hardware after the start is generated). writing a ?1? to sto while in master mode will cause the interface to generate a stop and end the current transfer after the next ack cycle. if sto and sta are both set (while in master mode), a stop followed by a start will be generated. the arblost bit indicates that the interface has lost an arbitration. this may occur anytime the interface is transmitting (master or slave). a lost arbitratio n while operating as a slave indicates a bus error condi - tion. arblost is cleared by hardware each time si is cleared. the si bit (smbus interrupt flag) is set at the beginnin g and end of each transfer, after each byte frame, or when an arbitration is lost; see ta b l e 21.3 for more details. important note about the si bit: the smbus interface is stalled while si is set; thus scl is held low, and the bus is stalled until software clears si. 21.4.2.1.software ack generation when the ehack bit in register smb0 adm is cleared to ?0?, the firmware on the device must detect incom - ing slave addresses and ack or nack the slave addres s and incoming data bytes. as a receiver, writing the ack bit defines the outgoing ack value; as a tr ansmitter, reading the ack bit indicates the value received during the last ack cycle. ackrq is set each ti me a byte is received, indi cating that an outgoing ack value is needed. when ackrq is set, software should write the desired outgoing value to the ack bit before clearing si. a nack will be g enerated if software does not writ e the ack bit before clearing si. sda will reflect the defined ack value immediately following a write to the ack bit; however scl will remain low until si is cleared. if a received slave address is not acknow ledged, further slave events will be ignored until the next start is detected. 21.4.2.2.hardwar e ack generation when the ehack bit in regi ster smb0adm is set to ?1?, automati c slave address recognition and ack gen - eration is enabled. more detail about automatic slave address recognition can be found in section 21.4.3 . as a receiver, the value currently specified by the ac k bit will be automatically sent on the bus during the ack cycle of an incoming data byte. as a transmitter, reading the ack bit indicates the value received on the last ack cycle. the ackrq bit is not used when hardware ack generation is enabled. if a received slave address is nacked by hardware, further sl ave events will be ignored un til the next start is detected, and no interrupt will be generated. ta b l e 21.3 lists all sources for hardware changes to the smb0cn bits. refer to table 21.5 for smbus sta - tus decoding using the smb0cn register.
sfr definition 21.2. smb0cn: smbus control bit 7 6 5 4 3 2 1 0 name type reset rev. 0.2 153 c8051f336/7/8/9 sfr address = 0xc0; bit-addressable bit name description read write 7 master smbus master/slave indicator. this read-only bit indicates when the smbus is operating as a master. 0: smbus operating in slave mode. 1: smbus operating in master mode. n/a 6 txmode smbus transmit mode indicator. this read-only bit indicates when the smbus is operating as a transmitter. 0: smbus in receiver mode. 1: smbus in transmitter mode. n/a 5 sta smbus start flag. 0: no start or repeated start detected. 1: start or repeated start detected. 0: no start generated. 1: when configured as a master, initiates a start or repeated start. 4 sto smbus stop flag. 0: no stop condition detected. 1: stop condition detected (if in slave mode) or pend - ing (if in master mode). 0: no stop condition is transmitted. 1: when configured as a master, causes a stop condition to be transmit - ted after the next ack cycle. cleared by hardware. 3 ackrq smbus acknowledge request. 0: no ack requested 1: ack requested n/a 2 arblost smbus arbitration lost indicator. 0: no arbitration error. 1: arbitration lost n/a 1 ack smbus acknowledge. 0: nack received. 1: ack received. 0: send nack 1: send ack 0 si smbus interrupt flag. this bit is set by hardware under the conditions listed in table 15.3. si must be cleared by software. while si is set, scl is held low and the smbus is stalled. 0: no interrupt pending 1 : interrupt pending 0: clear interrupt, and ini - tiate next state machine event. 1: force interrupt. master txmode sta sto ackrq arblost ack si rrr/wr/wrrr/wr/w 00000000
table 21.3. sources for hardware changes to smb0cn ? a start is generated. ? a stop is generated. ? arbitration is lost. ? start is generated. ? smb0dat is written before the start of an smbus frame. ? a start is detected. ? arbitration is lost. ? smb0dat is not written before the start of an smbus frame. ? a start followed by an address byte is received. ? must be cleared by software. ? a stop is detected while addressed as a slave. ? arbitration is lost due to a detected stop. ? a pending stop is generated. ? a byte has been received and an ack response value is needed (only when hard - ware ack is not enabled). ? after each ack cycle. ? a repeated start is detected as a master when sta is low (unwanted repeated start). ? scl is sensed low while attempting to gener - ate a stop or repeated start condition. ? sda is sensed low while transmitting a ?1? (excluding ack bits). ? each time si is cleared. ? the incoming ack value is low (acknowledge). ? the incoming ack value is high (not acknowledge). ? a start has been generated. ? lost arbitration. ? a byte has been transmitted and an ack/nack received. ? a byte has been received. ? a start or repeated start followed by a slave address + r/w has been received. ? a stop has been received. ? must be cleared by software. c8051f336/7/8/9 154 rev. 0.2 bit set by hardware when: cleared by hardware when: master txmode sta sto ackrq arblost ack si
rev. 0.2 155 c8051f336/7/8/9 21.4.3. hardware slave address recognition the smbus hardware has the capability to automatically recognize incoming slav e addresses and send an ack without software intervention. automatic slave address recognition is enabled by setting the ehack bit in register smb0adm to ?1?. this will enable both automatic slave address recognition and automatic hardware ack generation for received bytes (as a mast er or slave). more detail on automatic hardware ack generation can be found in section 21.4.2.2 . the registers used to define which address(es) ar e recognized by the hardware are the smbus slave address register ( sfr definition 21.3 ) and the smbus slave address mask register ( sfr definition 21.4 ). a single address or range of addresses (including the general call address 0x00) can be specified using these two registers. the most-significant seven bits of the two registers are used to define which addresses will be acked. a ?1? in bit positions of the slave address mask slvm[6 :0] enable a comparison between the received slave address and the hardware?s slave address slv[6:0] for those bits. a ?0? in a bit of the slave address mask means that bit will be treated as a ?don?t care ? for comparison purposes. in this case, either a ?1? or a ?0? value are acceptable on th e incoming slave address. additionally, if the gc bit in register smb0adr is set to ?1?, hardware will recognize th e general call address (0x00). ta b l e 21.4 shows some example parame ter settings and the slave addresses t hat will be recognized by hardware under those conditions. table 21.4. hardware address recogni tion examples (ehack = 1) hardware slave address slv[6:0] slave address mask slvm[6:0] gc bit slave addresses recognized by hardware 0x34 0x7f 0 0x34 0x34 0x7f 1 0x34, 0x00 (general call) 0x34 0x7e 0 0x34, 0x35 0x34 0x7e 1 0x34, 0x35, 0x00 (general call) 0x70 0x73 0 0x70, 0x74, 0x78, 0x7c
sfr definition 21.3. smb0adr: smbus slave address bit 7 6 5 4 3 2 1 0 name slv[6:0] gc type r/w r/w reset 0 0 0 0 0 0 0 0 c8051f336/7/8/9 156 rev. 0.2 sfr address = 0xd7 bit name function 7:1 slv[6:0] smbus hardware slave address. defines the smbus slave address(es) for automatic hardware acknowledgement. only address bits which have a ?1? in the corresponding bit position in slvm[6:0] are checked against the incoming address. this allows multiple addresses to be recognized. 0 gc general call address enable. when hardware address reco gnition is enabled (ehack = 1), this bit will deter - mine whether the general call address (0 x00) is also recognized by hardware. 0: general call ad dress is ignored. 1: general call address is recognized. sfr definition 21.4. smb0adm: smbus slave address mask bit 7 6 5 4 3 2 1 0 name slvm[6:0] ehack type r/w r/w reset 1 1 1 1 1 1 1 0 sfr address = 0xe7 bit name function 7:1 slvm[6:0] smbus slave address mask. defines which bits of register smb0adr are compared with an incoming address byte, and which bits are ignored. any bit set to ?1? in slvm[6:0] enables compari - sons with the corresponding bit in slv[6:0]. bits set to ?0? are ignored (can be either ?0? or ?1? in the incoming address). 0 ehack hardware acknowledge enable. enables hardware acknowledgement of slave address and received data bytes. 0: firmware must manually acknowledge all incoming address and data bytes. 1: automatic slave address recognition and hardware acknowledge is enabled.
rev. 0.2 157 c8051f336/7/8/9 21.4.4. data register the smbus data register smb0dat holds a byte of serial data to be transmitted or one that has just been received. software may safely read or write to the data register when the si flag is set. software should not attempt to access the smb0dat register when the smbus is enabled and the si flag is cleared to logic 0, as the interface may be in the process of shifting a byte of data into or out of the register. data in smb0dat is always shifted ou t msb first. after a byte has been received, the first bit of received data is located at the msb of smb0dat. while data is being shifted out, data on the bus is simultaneously being shifted in. smb0dat always contains the last data byte present on the bus. in the event of lost arbi - tration, the transition from master transmitter to slave receiver is made with the correct data or address in smb0dat. sfr definition 21.5. smb0dat: smbus data bit 7 6 5 4 3 2 1 0 name smb0dat[7:0] type r/w reset 0 0 0 0 0 0 0 0 sfr address = 0xc2 bit name function 7:0 smb0dat[7:0] smbus data. the smb0dat register contains a byte of data to be transmitted on the smbus serial interface or a byte that has just b een received on the smbus serial interface. the cpu can read from or write to this regi ster whenever the si serial interrupt flag (smb0cn.0) is set to logic 1. the serial data in the register remains stable as long as the si flag is set. when the si flag is not set, the system may be in the process of shifting data in/out and the cpu shou ld not attempt to access this register.
c8051f336/7/8/9 158 rev. 0.2 21.5. smbus transfer modes the smbus interface may be configured to operate as master and/or slave. at any particular time, it will be operating in one of the following four modes: master transmitter, master receiver, slave transmitter, or slave receiver. the smbus interface enters master mo de any time a start is generated, and remains in master mode until it loses an arbitration or generates a stop. an smbus interrupt is generated at the end of all smbus byte frames. note that the position of the ack interrupt when operating as a receiver depends on whether hardware ack generation is enabled . as a receiver, the inte rrupt for an ack occurs before the ack with hardware ack generation disabled, and after the ack when hardware ack genera - tion is enabled. as a transmitter, interrupts occur after the ack, regardless of whether hardware ack gen - eration is enabled or not. 21.5.1. write sequence (master) during a write sequence, an smbus mast er writes data to a slave device. the master in this transfer will be a transmitter during the address byte, and a transmitter during all data bytes. the smbus interface gener - ates the start condition and transmits the first byte containing the address of the target slave and the data direction bit. in this case th e data direction bit (r/w) will be logic 0 (write). the master then trans - mits one or more bytes of serial data. after each byte is transmitted, an acknowledge bit is generated by the slave. the transfer is ended wh en the sto bit is set and a stop is generated. note that the interface will switch to master receiver mode if smb0dat is not written followin g a master transm itter interrupt. figure 21.5 shows a typical master write sequence. two tr ansmit data bytes are shown, though any num - ber of bytes may be transmitted. notice that all of the ?data byte transferred? interrupts occur after the ack cycle in this mode, regardless of whether hardware ack generation is enabled. a a a s w p data byte data byte sla s = start p = stop a = ack w = write sla = slave address received by smbus interface transmitted by smbus interface interrupts with hardware ack disabled (ehack = 0) interrupts with hardware ack enabled (ehack = 1) figure 21.5. typical m aster write sequence
rev. 0.2 159 c8051f336/7/8/9 21.5.2. read sequence (master) during a read sequence, an smbus ma ster reads data from a slave devic e. the master in this transfer will be a transmitter during the address byte, and a receiv er during all data bytes. the smbus interface gener - ates the start condition and transmits the first byte containing the address of the target slave and the data direction bit. in this case t he data direction bit (r/w) will be logic 1 (read). serial data is then received from the slave on sda while the smbus outputs the serial clock. the slave transmits one or more bytes of serial data. if hardware ack generation is disabled, the ackrq is se t to ?1? and an interrupt is generated after each received byte. software must writ e the ack bit at that time to ack or nack the received byte. with hardware ack generation enab led, the smbus hardware will autom atically generate the ack/nack, and then post the interrupt. it is important to note that the appropriate ack or nack value should be set up by the software prior to receiving the byte when hardware ack generation is enabled. writing a ?1? to the ack bit generates an ack; writi ng a ?0? generates a nack. so ftware should write a ?0? to the ack bit for the last data tr ansfer, to transmit a nack. the inte rface exits master receiver mode after the sto bit is set and a stop is generated. the in terface will switch to master transmitter mode if smb0dat is written while an active master receiver. figure 21.6 shows a typical master read sequence. two received data bytes are shown, though any number of bytes may be received. notice that the ?data byte transferred? interrupts occur at different places in the sequence, depending on whether hardware ack generation is enabled. the interrupt occurs before the ack with hardware ack generation disabled, and after the ack when hardware ack generation is enabled. data byte data byte a n a s r p sla s = start p = stop a = ack n = nack r = read sla = slave address received by smbus interface transmitted by smbus interface interrupts with hardware ack disabled (ehack = 0) interrupts with hardware ack enabled (ehack = 1) figure 21.6. typical master read sequence
c8051f336/7/8/9 160 rev. 0.2 21.5.3. write sequence (slave) during a write sequence, an smbus ma ster writes data to a slave device. the slave in this transfer will be a receiver during the address byte, and a receiver during all data bytes. when slave events are enabled (inh = 0), the interface enters slave receiver mode when a start followed by a slave address and direc - tion bit (write in this case) is received. if hardware ack generation is disabled, upon entering slave receiver mode, an interrupt is generated and the ac krq bit is set. the software must respond to the received slave address with an ack, or ignore the received slave address with a nack. if hardware ack generation is enabled, th e hardware will apply the ac k for a slave address which matches the criteria set up by smb0adr and smb0adm. the inte rrupt will occur after the ack cycle. if the received slave address is ignore d (by software or hardware), slav e interrupts will be in hibited until the next start is detected. if the received slave address is acknowledged, zero or more data bytes are received. if hardware ack generation is disabled, the ackrq is se t to ?1? and an interrupt is generated after each received byte. software must writ e the ack bit at that time to ack or nack the received byte. with hardware ack generation enab led, the smbus hardware will autom atically generate the ack/nack, and then post the interrupt. it is important to note that the appropriate ack or nack value should be set up by the software prior to receiving the byte when hardware ack generation is enabled. the interface exits slave re ceiver mode after receiving a stop. note that the interface will switch to slave transmitter mode if smb0 dat is written while an active slave receiver. figure 21.7 shows a typical slave write sequence. two received data bytes are shown, though any number of bytes may be received. notice that the ?data byte transferred? interrupts occur at different places in the sequence, depending on whether hardware ack generation is enabled. the interrupt occurs before the ack with hardware ack generation disabled, and after the ack when hardware ack generation is enabled. p w sla s data byte data byte a a a s = start p = stop a = ack w = write sla = slave address received by smbus interface transmitted by smbus interface interrupts with hardware ack disabled (ehack = 0) interrupts with hardware ack enabled (ehack = 1) figure 21.7. typical slave write sequence
rev. 0.2 161 c8051f336/7/8/9 21.5.4. read sequence (slave) during a read sequence, an smbus ma ster reads data from a slave device. the slave in this transfer will be a receiver during the address byte, and a transm itter during all data bytes. when slave events are enabled (inh = 0), the interface enters slave receiver mode (to receive the slave address) when a start followed by a slave address and direction bit (read in this case) is received. if hardware ack generation is disabled, upon entering slave receiver mode, an interrupt is generated and the ackrq bit is set. the software must respond to the received slave address with an ack, or ignore the received slave address with a nack. if hardware ack generat ion is enabled, the hardware will apply the ack for a slave address which matches the criteria set up by smb0adr and smb0adm. the interrupt will occur after the ack cycle. if the received slave address is ignore d (by software or hardware), slav e interrupts will be in hibited until the next start is detected. if the received slave address is acknowledged, zero or more data bytes are trans - mitted. if the received slave address is acknowledged, data should be written to smb0dat to be transmit - ted. the interface enters slave transmitter mode, and tr ansmits one or more bytes of data. after each byte is transmitted, the master sends an acknowledge bit; if the acknowledge bit is an ack, smb0dat should be written with the next data byte. if the acknowle dge bit is a nack, smb0dat should not be written to before si is cleared (note: an error condition may be generated if smb0dat is wr itten following a received nack while in slave transmitter mo de). the interface exits slave transmitter mode after receiving a stop. note that the interface will switch to slav e receiver mode if smb0dat is not written following a slave transmitter interrupt. figure 21.8 shows a typical slave read sequence. two transmitted data bytes are shown, though any number of byte s may be transmitted. notice that all of the ?data byte transferred? interrupts occur after the ack cycle in this mode, regardless of whether hardware ack generation is enabled. p r sla s data byte data byte a n a s = start p = stop n = nack r = read sla = slave address received by smbus interface transmitted by smbus interface interrupts with hardware ack disabled (ehack = 0) interrupts with hardware ack enabled (ehack = 1) figure 21.8. typical slave read sequence 21.6. smbus status decoding the current smbus status can be easily decoded usin g the smb0cn register. the appropriate actions to take in response to an smbus event depend on whether hardware slave address recognition and ack generation is enabled or disabled. ta b l e 21.5 describes the typical actions when hardware slave address recognition and ack generation is disabled. ta b l e 21.6 describes the typical actions when hardware slave address recognition and ack generation is enabled. in the tables, status vector refers to the four upper bits of smb0cn: master, tx mode, sta, and sto. the shown response options are only the typ -
c8051f336/7/8/9 162 rev. 0.2 ical responses; application-specific procedures are allo wed as long as they conform to the smbus specifi - cation. highlighted responses are allowed by hardwar e but do not conform to the smbus specification. table 21.5. smbus status decoding with hard ware ack generation disabled (ehack = 0) mode values read current smbus state typical response options values to write next status vector expected status vector ackrq arblost ack sta sto ack master transmitter 1110 0 0 x a master start was gener - ated. load slave address + r/w into smb0dat. 00x1100 1100 000 a master data or address byte was transmitted; nack received. set sta to restart transfer. 10x1110 abort transfer. 01x - 001 a master data or address byte was transmitted; ack received. load next data byte into smb0dat. 00x1100 end transfer with stop. 01x - end transfer with stop and start another transfer. 11x - send repeated start. 10x1110 switch to master receiver mode (clear si without writing new data to smb0dat). 0 0 x 1000 master receiver 1000 1 0 x a master data byte was received; ack requested. acknowledge received byte; read smb0dat. 0 0 1 1000 send nack to indi cate last byte, and send stop. 010 - send nack to indi cate last byte, and send stop followed by start. 1101110 send ack followed by repeated start. 1011110 send nack to indi cate last byte, and send repeated start. 1001110 send ack and switch to master transmitter mode (write to smb0dat before clearing si). 0 0 1 1100 send nack and switch to mas - ter transmitter mode (write to smb0dat before clearing si). 0 0 0 1100
rev. 0.2 163 c8051f336/7/8/9 slave transmitter 0100 000 a slave byte was transmitted; nack received. no action required (expecting stop condition). 0 0 x 0001 001 a slave byte was transmitted; ack received. load smb0dat with next data byte to transmit. 0 0 x 0100 01x a slave byte was transmitted; error detected. no action required (expecting master to end transfer). 0 0 x 0001 0101 0 x x an illegal stop or bus error was detected while a slave transmission was in progress. clear sto. 00x - slave receiver 0010 10x a slave address + r/w was received; ack requested. if write, ackno wledge received address 0 0 1 0000 if read, load smb0dat with data byte; ack received address 0 0 1 0100 nack received address. 000 - 11x lost arbitration as master; slave address + r/w received; ack requested. if write, ackno wledge received address 0 0 1 0000 if read, load smb0dat with data byte; ack received address 0 0 1 0100 nack received address. 000 - reschedule failed transfer; nack received address. 1001110 0001 00x a stop was detected while addressed as a slave trans - mitter or slave receiver. clear sto. 00x - 11x lost arbitration while attempt - ing a stop. no action required (transfer complete/aborted). 000 - 0000 1 0 x a slave byte was received; ack requested. acknowledge received byte; read smb0dat. 0 0 1 0000 nack received byte. 000 - bus error condition 0010 0 1 x lost arbitration while attempt - ing a repeated start. abort failed transfer. 00x - reschedule failed transfer. 10x1110 0001 0 1 x lost arbitration due to a detected stop. abort failed transfer. 00x - reschedule failed transfer. 10x1110 0000 1 1 x lost arbitration while transmit - ting a data byte as master. abort failed transfer. 000 - reschedule failed transfer. 1001110 table 21.5. smbus status decoding with hardware ack generation disabled (ehack = 0) (continued) mode values read current smbus state typical response options values to write next status vector expected status vector ackrq arblost ack sta sto ack
c8051f336/7/8/9 164 rev. 0.2 table 21.6. smbus status decoding with ha rdware ack generation enabled (ehack = 1) mode values read current smbus state typical response options values to write next status vector expected status vector ackrq arblost ack sta sto ack master transmitter 1110 0 0 x a master start was gener - ated. load slave address + r/w into smb0dat. 00x1100 1100 000 a master data or address byte was transmitted; nack received. set sta to restart transfer. 10x1110 abort transfer. 01x - 001 a master data or address byte was transmitted; ack received. load next data byte into smb0dat. 00x1100 end transfer with stop. 01x - end transfer with stop and start another transfer. 11x - send repeated start. 10x1110 switch to master receiver mode (clear si without writing new data to smb0dat). set ack for initial data byte. 0 0 1 1000 master receiver 1000 001 a master data byte was received; ack sent. set ack for next data byte; read smb0dat. 0 0 1 1000 set nack to indicate next data byte as the last data byte; read smb0dat. 0 0 0 1000 initiate repeated start. 1001110 switch to master transmitter mode (write to smb0dat before clearing si). 0 0 x 1100 000 a master data byte was received; nack sent (last byte). read smb0dat; send stop. 010 - read smb0dat; send stop followed by start. 1101110 initiate repeated start. 1001110 switch to master transmitter mode (write to smb0dat before clearing si). 0 0 x 1100
rev. 0.2 165 c8051f336/7/8/9 slave transmitter 0100 000 a slave byte was transmitted; nack received. no action required (expecting stop condition). 0 0 x 0001 001 a slave byte was transmitted; ack received. load smb0dat with next data byte to transmit. 0 0 x 0100 01x a slave byte was transmitted; error detected. no action required (expecting master to end transfer). 0 0 x 0001 0101 0 x x an illegal stop or bus error was detected while a slave transmission was in progress. clear sto. 00x - slave receiver 0010 00x a slave address + r/w was received; ack sent. if write, set ack for first data byte. 0 0 1 0000 if read, load smb0dat with data byte 0 0 x 0100 01x lost arbitration as master; slave address + r/w received; ack sent. if write, set ack for first data byte. 0 0 1 0000 if read, load smb0dat with data byte 0 0 x 0100 reschedule failed transfer 10x1110 0001 00x a stop was detected while addressed as a slave trans - mitter or slave receiver. clear sto. 00x - 01x lost arbitration while attempt - ing a stop. no action required (transfer complete/aborted). 000 - 0000 0 0 x a slave byte was received. set ack for next data byte; read smb0dat. 0 0 1 0000 set nack for next data byte; read smb0dat. 0 0 0 0000 bus error condition 0010 0 1 x lost arbitration while attempt - ing a repeated start. abort failed transfer. 00x - reschedule failed transfer. 10x1110 0001 0 1 x lost arbitration due to a detected stop. abort failed transfer. 00x - reschedule failed transfer. 10x1110 0000 0 1 x lost arbitration while transmit - ting a data byte as master. abort failed transfer. 00x - reschedule failed transfer. 10x1110 table 21.6. smbus status decoding wi th hardware ack generation enabled (ehack = 1) (continued) mode values read current smbus state typical response options values to write next status vector expected status vector ackrq arblost ack sta sto ack
c8051f336/7/8/9 166 rev. 0.2 22. uart0 uart0 is an asynchronous, full duplex serial port offering modes 1 and 3 of the standard 8051 uart. enhanced baud rate support allows a wide range of clock sources to generate standard baud rates (details in section ?22.1. enhanced baud rate generation? on page 167 ). received data buffering allows uart0 to start reception of a second incoming data byte be fore software has finished reading the previous data byte. uart0 has two associated sfrs: serial control regist er 0 (scon0) and serial data buffer 0 (sbuf0). the single sbuf0 location provides access to both transmit and receive registers. writes to sbuf0 always access the transmit register. reads of sbuf0 always access the buffered receive register; it is not possible to read data from the transmit register. with uart0 interrupts enabled, an interrupt is generated each time a transmit is completed (ti0 is set in scon0), or a data byte has been received (ri0 is set in scon0). the uart0 interrupt flags are not cleared by hardware when the cpu vectors to the interr upt service routine. they must be cleared manually by software, allowing software to determine the cause of the uart0 interrupt (transmit complete or receive complete). uart baud rate generator ri scon ri ti rb8 tb8 ren mce smode tx control tx clock send sbuf (tx shift) start data write to sbuf crossbar tx shift zero detector tx irq set q d clr stop bit tb8 sfr bus serial port interrupt ti port i/o rx control start rx clock load sbuf shift 0x1ff rb8 rx irq input shift register (9 bits) load sbuf read sbuf sfr bus crossbar rx sbuf (rx latch) figure 22.1. uart0 block diagram
rev. 0.2 167 c8051f336/7/8/9 22.1. enhanced baud rate generation the uart0 baud rate is generated by timer 1 in 8-bit auto-reload mode. the tx clock is generated by tl1; the rx clock is generated by a copy of tl1 (shown as rx timer in figure 22.2 ), which is not user- accessible. both tx and rx timer overflows are divid ed by two to generate the tx and rx baud rates. the rx timer runs when timer 1 is enabled, and uses the same reload value (th1). however, an rx timer reload is forced when a start condition is de tected on the rx pin. th is allows a receive to begin any time a start is detected, independent of the tx timer state. rx timer start detected overflow overflow th1 tl1 tx clock 2 rx clock 2 timer 1 uart figure 22.2. uart0 baud rate logic timer 1 should be configured for mode 2, 8-bit auto-reload (see section ?24.1.3. mode 2: 8-bit counter/timer with auto-reload? on page 191 ). the timer 1 reload value should be set so that overflows will occur at two times the desired uart ba ud rate frequency. note that timer 1 may be clocked by one of six sources: sysclk, sysclk / 4, sysclk / 12, sysclk / 48, the external oscillator clock / 8, or an external input t1. for any given timer 1 clock source, the uart0 baud rate is determined by equation 22.1 -a and equation 22.1 -b. uartbaudrate 1 2 -- - t1_overflow_rate = t1_overflow_rate t1 clk 256 th1 ? ------------ ------------- - = a) b) equation 22.1. uart0 baud rate where t1 clk is the frequency of the clock supplied to timer 1, and t1h is the high byte of timer 1 (reload value). timer 1 clock frequency is selected as described in section ?24. timers? on page 187 . a quick ref - erence for typical baud rates and syst em clock frequencies is given in ta b l e 22.1 through ta b l e 22.2 . note that the internal oscillator may still generate the system clock when the ex ternal oscillator is driving timer 1.
c8051f336/7/8/9 168 rev. 0.2 22.2. operational modes uart0 provides standard asynchronous, full duplex communication. the uart mode (8-bit or 9-bit) is selected by the s0mode bit (scon0.7). typical uart connection options are shown in figure 22.3 . or rs-232 c8051fxxx rs-232 level xltr tx rx c8051fxxx rx tx mcu rx tx figure 22.3. uart interconnect diagram 22.2.1. 8-bit uart 8-bit uart mode uses a total of 10 bits per data byte: one start bit, eight data bits (lsb first), and one stop bit. data are transmitted lsb first from the tx0 pin a nd received at the rx0 pin. on receive, the eight data bits are stored in sbuf0 and the stop bit goes into rb80 (scon0.2). data transmission begins wh en software writes a data byte to th e sbuf0 register. the ti0 transmit inter - rupt flag (scon0.1) is set at the end of the transmi ssion (the beginning of the stop-bit time). data recep - tion can begin any time after the ren0 rece ive enable bit (scon0.4) is set to logic 1. after the stop bit is received, the data byte w ill be loaded into the sbuf0 re ceive register if the follo wing conditions are met: ri0 must be logic 0, and if mce0 is logic 1, the stop bit must be logic 1. in the event of a receive data over - run, the first received 8 bits are latched into the sbuf0 receive register and the following overrun data bits are lost. if these conditions are met, the eight bits of data is stor ed in sbuf0, the stop bit is stored in rb80 and the ri0 flag is set. if these conditio ns are not met, sbuf0 and rb80 will no t be loaded and the ri0 flag will not be set. an interrupt will occur if enabled when ei ther ti0 or ri0 is set. d1 d0 d2 d3 d4 d5 d6 d7 start bit mark stop bit bit times bit sampling space figure 22.4. 8-bit u art timing diagram
rev. 0.2 169 c8051f336/7/8/9 22.2.2. 9-bit uart 9-bit uart mode uses a total of eleven bits per data byte: a start bit, 8 data bits (lsb first), a programma - ble ninth data bit, and a stop bit. the state of the nint h transmit data bit is determ ined by the value in tb80 (scon0.3), which is assigned by user software. it can be assigned the value of the parity flag (bit p in reg - ister psw) for error detection, or used in multiprocessor communications. on receive, the ninth data bit goes into rb80 (scon0.2) and the stop bit is ignored. data transmission begins when an instruction writes a data byte to the sbuf0 register. the ti0 transmit interrupt flag (scon0.1) is set at the end of the tran smission (the beginning of the stop-bit time). data reception can begin any time after the ren0 receive en able bit (scon0.4) is set to ?1?. after the stop bit is received, the data byte will be lo aded into the sbuf0 receiv e register if the followin g conditions are met: (1) ri0 must be logic 0, and (2) if mce0 is logic 1, the 9th bit must be logic 1 (when mce0 is logic 0, the state of the ninth data bit is unimportant). if these cond itions are met, the eight bits of data are stored in sbuf0, the ninth bit is stored in rb80, and the ri0 flag is set to ?1?. if the above conditions are not met, sbuf0 and rb80 will not be loaded and the ri0 flag will not be set to ?1?. a ua rt0 interrupt will occur if enabled when either ti0 or ri0 is set to ?1?. d1 d0 d2 d3 d4 d5 d6 d7 start bit mark stop bit bit times bit sampling space d8 figure 22.5. 9-bit u art timing diagram 22.3. multiprocessor communications 9-bit uart mode supports multiprocessor communication between a master processor and one or more slave processors by special use of t he ninth data bit. when a master processor wants to transmit to one or more slaves, it first sends an address byte to select th e target(s). an address byte differs from a data byte in that its ninth bit is logic 1; in a data byte, the ninth bit is always set to logic 0. setting the mce0 bit (scon0.5) of a slave processor co nfigures its uart such that when a stop bit is received, the uart will gener ate an interrupt only if the ninth bit is logic 1 (rb80 = 1) signifying an address byte has been received. in the ua rt interrupt handler, software will compare the received address with the slave's own assigned 8-bit addre ss. if the addresses match, the slav e will clear its mce0 bit to enable interrupts on the reception of the following data byte (s). slaves that weren't addressed leave their mce0 bits set and do not generate interrupts on the reception of the following data bytes, thereby ignoring the data. once the entire message is received, the addres sed slave resets its mce0 bit to ignore all transmis - sions until it receives the next address byte. multiple addresses can be assigned to a single sl ave and/or a single address can be assigned to multiple slaves, thereby enabling "broadcast" transmissions to more than one slave simultaneously. the master processor can be configured to receive all transmissi ons or a protocol can be implemented such that the master/slave role is tem porarily reversed to enable half-duplex transmission between the original master and slave(s).
master device slave device tx rx rx tx slave device rx tx slave device rx tx v+ c8051f336/7/8/9 170 rev. 0.2 figure 22.6. uart multi-processor mode interconnect diagram
sfr definition 22.1. scon0: serial port 0 control bit 7 6 5 4 3 2 1 0 name s0mode mce0 ren0 tb80 rb80 ti0 ri0 type r/w r r/w r/w r/w r/w r/w r/w reset 0 1 0 0 0 0 0 0 rev. 0.2 171 c8051f336/7/8/9 sfr address = 0x98; bit-addressable bit name function 7 s0mode serial port 0 operation mode. selects the uart0 operation mode. 0: 8-bit uart with variable baud rate. 1: 9-bit uart with variable baud rate. 6 unused unused. read = 1b, write = don?t care. 5 mce0 multiprocessor comm unication enable. the function of this bit is dependent on the serial port 0 operation mode: mode 0: checks for valid stop bit. 0: logic level of stop bit is ignored. 1: ri0 will only be activated if stop bit is logic level 1. mode 1: multiprocessor communications enable. 0: logic level of ninth bit is ignored. 1: ri0 is set and an interrupt is gene rated only when the ninth bit is logic 1. 4 ren0 receive enable. 0: uart0 reception disabled. 1: uart0 reception enabled. 3 tb80 ninth transmission bit. the logic level of this bit will be sent as the ninth transmission bi t in 9-bit uart mode (mode 1). unused in 8-bit mode (mode 0). 2 rb80 ninth receive bit. rb80 is assigned the value of the stop bit in mode 0; it is assigned the value of the 9th data bit in mode 1. 1 ti0 transmit interrupt flag. set by hardware when a byte of data has been transmitted by uart0 (after the 8th bit in 8-bit uart mode, or at the beginning of the stop bit in 9-bit uart mode). when the uart0 interrupt is enabled, setting this bit causes the cpu to vector to the uart0 interrupt service routine. this bit must be cleared manually by software. 0 ri0 receive interrupt flag. set to ?1? by hardware when a byte of data has been received by uart0 (set at the stop bit sampling time). when the uart0 inte rrupt is enabled, se tting this bit to ?1? causes the cpu to vector to the uart0 in terrupt service routine. this bit must be cleared manually by software.
sfr definition 22.2. sbuf0: serial (uart0) port data buffer bit 7 6 5 4 3 2 1 0 name sbuf0[7:0] type r/w reset 0 0 0 0 0 0 0 0 c8051f336/7/8/9 172 rev. 0.2 sfr address = 0x99 bit name function 7:0 sbuf0[7:0] serial data buffer bits 7?0 (msb?lsb) this sfr accesses two registers; a transmit shift register and a receive latch register. when data is written to sbuf0, it goes to the transmit shift register and is held for serial transmission. writing a byte to sbuf0 initiates the transmission. a read of sbuf0 returns the contents of the receive latch.
table 22.1. timer settings for standard baud rates using the internal 24.5 mhz oscillator sysclk from internal osc. notes: 1. sca1 ? sca0 and t1m bit definitions can be found in section 24.1 . 2. x = don?t care. table 22.2. timer settings for standard baud rates using an external 22.1184 mhz oscillator sysclk from external osc. sysclk from internal osc. notes: 1. sca1 ? sca0 and t1m bit definitions can be found in section 24.1 . 2. x = don?t care. rev. 0.2 173 c8051f336/7/8/9 frequency: 24.5 mhz target baud rate (bps) baud rate % error oscilla- tor divide factor timer clock source sca1?sca0 (pre-scale select) 1 t1m 1 timer 1 reload value (hex) 230400 ?0.32% 106 sysclk xx 2 1 0xcb 115200 ?0.32% 212 sysclk xx 1 0x96 57600 0.15% 426 sysclk xx 1 0x2b 28800 ?0.32% 848 sysclk/4 01 0 0x96 14400 0.15% 1704 sysclk/12 00 0 0xb9 9600 ?0.32% 2544 sysclk/12 00 0 0x96 2400 ?0.32% 10176 sysclk/48 10 0 0x96 1200 0.15% 20448 sysclk/48 10 0 0x2b frequency: 22.1184 mhz target baud rate (bps) baud rate % error oscilla- tor divide factor timer clock source sca1?sca0 (pre-scale select) 1 t1m 1 timer 1 reload value (hex) 230400 0.00% 96 sysclk xx 2 10xd0 115200 0.00% 192 sysclk xx 1 0xa0 57600 0.00% 384 sysclk xx 1 0x40 28800 0.00% 768 sysclk / 12 00 0 0xe0 14400 0.00% 1536 sysclk / 12 00 0 0xc0 9600 0.00% 2304 sysclk / 12 00 0 0xa0 2400 0.00% 9216 sysclk / 48 10 0 0xa0 1200 0.00% 18432 sysc lk / 48 10 0 0x40 230400 0.00% 96 extclk / 8 11 0 0xfa 115200 0.00% 192 extclk / 8 11 0 0xf4 57600 0.00% 384 extclk / 8 11 0 0xe8 28800 0.00% 768 extclk / 8 11 0 0xd0 14400 0.00% 1536 extclk / 8 11 0 0xa0 9600 0.00% 2304 extclk / 8 11 0 0x70
c8051f336/7/8/9 174 rev. 0.2 23. enhanced serial peri pheral interface (spi0) the enhanced serial peripheral interface (spi0) prov ides access to a flexible, full-duplex synchronous serial bus. spi0 can operate as a master or slave device in both 3-wire or 4-wire modes, and supports mul - tiple masters and slaves on a single spi bus. the slave-select (nss) signal can be configured as an input to select spi0 in slave mode, or to disable master mode operation in a multi-master environment, avoiding contention on the spi bus when more than one master attempts simultaneous data transfers. nss can also be configured as a chip-select output in master mode, or disabled for 3-wire operation. additional gen - eral purpose port i/o pins can be used to se lect multiple slave dev ices in master mode. sfr bus data path control sfr bus write spi0dat receive data buffer spi0dat 0 1 2 3 4 5 6 7 shift register spi control logic spi0ckr scr7 scr6 scr5 scr4 scr3 scr2 scr1 scr0 spi0cfg spi0cn pin interface control pin control logic c r o s s b a r port i/o read spi0dat spi irq tx data rx data sck mosi miso nss transmit data buffer clock divide logic sysclk ckpha ckpol slvsel nssmd1 nssmd0 spibsy msten nssin srmt rxbmt spif wcol modf rxovrn txbmt spien figure 23.1. spi block diagram
rev. 0.2 175 c8051f336/7/8/9 23.1. signal descriptions the four signals used by spi0 (mosi, miso, sck, nss) are described below. 23.1.1. master out, slave in (mosi) the master-out, slave-in (mosi) signal is an output fr om a master device and an input to slave devices. it is used to serially transfer data from the master to th e slave. this signal is an output when spi0 is operat - ing as a master and an input when spi0 is operating as a slave. data is transferred most-significant bit first. when configured as a master, mosi is driven by the msb of the shift register in both 3- and 4-wire mode. 23.1.2. master in, slave out (miso) the master-in, slave-out (miso) signal is an output from a slave device and an input to the master device. it is used to serially transfer data from the slave to the master. this signal is an input when spi0 is operat - ing as a master and an output when spi0 is operating as a slave. data is transferred most-significant bit first. the miso pin is placed in a high-impedance stat e when the spi module is disabled and when the spi operates in 4-wire mode as a slave that is not select ed. when acting as a slave in 3-wire mode, miso is always driven by the msb of the shift register. 23.1.3. serial clock (sck) the serial clock (sck) signal is an output from the mast er device and an input to slave devices. it is used to synchronize the transfer of data between the mast er and slave on the mosi and miso lines. spi0 gen - erates this signal when operating as a master. the sck signal is ignored by a spi slave when the slave is not selected (nss = 1) in 4-wire slave mode. 23.1.4. slave select (nss) the function of the slave-select (nss) signal is dependent on the setting of the nssmd1 and nssmd0 bits in the spi0cn register. there are three possib le modes that can be selected with these bits: 1. nssmd[1:0] = 00: 3-wire master or 3-wire slave mode: spi0 operates in 3-wire mode, and nss is disabled. when operating as a slave dev ice, spi0 is always selected in 3-wire mode. since no select signal is present, spi0 must be the only slave on the bus in 3-wire mode. this is intended for point-to-point communica tion between a master and one slave. 2. nssmd[1:0] = 01: 4-wire slave or multi-ma ster mode: spi0 operates in 4-wire mode, and nss is enabled as an input. when operating as a slave, nss selects the spi0 device. when operating as a master, a 1-to-0 transition of th e nss signal disables t he master function of spi0 so that multiple master devices can be used on the same spi bus. 3. nssmd[1:0] = 1x: 4-wire master mode: spi0 oper ates in 4-wire mode, and nss is enabled as an output. the setting of nssm d0 determines what logic leve l the nss pin will output. this configuration should only be used wh en operating spi0 as a master device. see figure 23.2, figure 23.3, and figure 23.4 for typical connection diag rams of the various operational modes. note that the setting of nssmd bits affects the pinout of the device. when in 3-wire master or 3-wire slave mode, the nss pin will not be mapped by the crossbar. in all other modes, the nss signal will be mapped to a pin on the device. see section ?20. port input/output? on page 126 for general purpose port i/o and crossbar information.
c8051f336/7/8/9 176 rev. 0.2 23.2. spi0 master mode operation a spi master device initiates all data transfers on a spi bus. spi0 is placed in master mode by setting the master enable flag (msten, spi0cn.6). writing a byte of data to the spi0 data register (spi0dat) when in master mode writes to the transmit buffer. if the spi shift register is empty, the byte in the transmit buffer is moved to the shift register, and a data transfer begins. the spi0 master immediately shifts out the data serially on the mosi line while provid ing the serial clock on sck. the spi f (spi0cn.7) flag is set to logic 1 at the end of the transfer. if interrupts are enabl ed, an interrupt request is generated when the spif flag is set. while the spi0 master transf ers data to a slave on the mosi line, the addressed spi slave device simultaneously transfers the contents of its shift register to the spi master on the miso line in a full-duplex operation. therefore, the spif flag serves as both a transmit-complete and receive-data-ready flag. the data byte received from the slave is transferred msb-fi rst into the master's shift register. when a byte is fully shifted into the register, it is moved to the receive buffer where it can be read by the processor by reading spi0dat. when configured as a master, spi0 can operate in one of three different modes: multi-master mode, 3-wire single-master mode, and 4-wire single-master mode. the default, multi-master mode is active when nssmd1 (spi0cn.3) = 0 and nssmd0 (spi0cn.2) = 1. in this mode, nss is an input to the device, and is used to disable the master spi0 when another mast er is accessing the bus. when nss is pulled low in this mode, msten (spi0cn.6) and spien (spi0cn.0) ar e set to 0 to disable the spi master device, and a mode fault is generate d (modf, spi0cn.5 = 1). mode fault will gen erate an inte rrupt if e nabled. spi0 must be manually re-enabled in soft ware under these circumstances. in multi-master systems, devices will typically default to being slave devices while they are not acting as the system master device. in multi-mas - ter mode, slave devices can be addressed individua lly (if needed) using general-purpose i/o pins. figure 23.2 shows a connection diagram between two ma ster devices in mu ltiple-master mode. 3-wire single-master mode is active when nssmd1 (s pi0cn.3) = 0 and nssmd0 ( spi0cn.2) = 0. in this mode, nss is not used, and is not mapped to an exte rnal port pin through the crossbar. any slave devices that must be addressed in this mode should be selected using general-purpose i/o pins. figure 23.3 shows a connection diagram between a master dev ice in 3-wire master mode and a slave device. 4-wire single-master mode is active wh en nssmd1 (spi0cn.3) = 1. in this mode, nss is configured as an output pin, and can be used as a sl ave-select signal for a single spi dev ice. in this mode, the output value of nss is controlled (in software) with the bit nssm d0 (spi0cn.2). additional slave devices can be addressed using general-purpose i/o pins. figure 23.4 shows a connection diagram for a master device in 4-wire master mode and two slave devices.
master device 2 master device 1 mosi miso sck miso mosi sck nss gpio nss gpio slave device master device mosi miso sck miso mosi sck slave device master device mosi miso sck miso mosi sck nss nss gpio slave device mosi miso sck nss rev. 0.2 177 c8051f336/7/8/9 figure 23.2. multiple-master mode connect ion diagram figure 23.3. 3-wire singl e master and 3-wire singl e slave mode connection diagram figure 23.4. 4-wire singl e master mode and 4-wire slave mode connection diagram
c8051f336/7/8/9 178 rev. 0.2 23.3. spi0 slave mode operation when spi0 is enabled and not confi gured as a master, it will operate as a spi slave. as a slave, bytes are shifted in through the mosi pin a nd out through the miso pin by a ma ster device controlling the sck sig - nal. a bit counter in the spi0 logic counts sck edges. when 8 bits have been shifted through the shift reg - ister, the spif flag is set to logic 1, and the byte is copied into the receive buffer. data is read from the receive buffer by reading spi0dat. a slave device cannot initiate transfers. data to be transferred to the master device is pre-loaded into the shift register by writing to spi0dat. writes to spi0dat are double- buffered, and are placed in the transmit buffer first. if the shift register is empty, the contents of the transmit buffer will immediately be transferred into the shift register. when the sh ift register already contains data, the spi will load the shift register wi th the transmit buffer?s contents af ter the last sck edg e of the next (or current) spi transfer. when configured as a slave, spi0 can be configured for 4-wire or 3-wire operation. the default, 4-wire slave mode, is active when nssmd1 (spi0cn.3) = 0 and nssmd0 (spi0cn.2) = 1. in 4-wire mode, the nss signal is routed to a port pin and configured as a digital input. spi0 is enabl ed when nss is logic 0, and disabled when nss is logic 1. the bit counter is reset on a falling edge of n ss. note that the nss sig - nal must be driven low at least 2 system clocks before the first active edge of sck for each byte transfer. figure 23.4 shows a connection diagram between two slav e devices in 4-wire slave mode and a master device. 3-wire slave mode is active when nssmd1 (spi0cn. 3) = 0 and nssmd0 (spi0cn.2) = 0. nss is not used in this mode, and is not mapped to an external port pin through the crossbar. since there is no way of uniquely addressing the device in 3-wire slave mode , spi0 must be the only slav e device present on the bus. it is important to note that in 3-wire slave mode there is no external means of resetting the bit counter that determines when a full byte has been received. th e bit counter can only be reset by disabling and re- enabling spi0 with the spien bit. figure 23.3 shows a connection diagram between a slave device in 3- wire slave mode and a master device. 23.4. spi0 interrupt sources when spi0 interrupts are e nabled, the following four flags will gener ate an interrupt when they are set to logic 1: all of the following bits must be cleared by software. 1. the spi interrupt flag, spif (spi0cn.7) is set to logic 1 at the end of each byte transfer. this flag can occur in all spi0 modes. 2. the write collision flag, wcol (spi0cn.6) is set to logic 1 if a write to spi0dat is attempted when the transmit buffer has not been emptied to the spi shift register. when this occurs, the write to spi0dat will be ignored, and the transmi t buffer will not be written.this flag can occur in all spi0 modes. 3. the mode fault flag modf (spi0cn.5) is set to logic 1 when spi0 is configured as a master, and for multi-master mode and the nss pin is pulled low. when a mode fault occurs, the msten and spien bits in spi0cn are set to logi c 0 to disable spi0 and allow another master device to access the bus. 4. the receive overrun flag rxovrn (spi0cn.4) is set to logic 1 when configured as a slave, and a transfer is completed and the receive buffer still holds an unread byte from a previous transfer. the new byte is not transferred to the receive buffer, allowing the previously received data byte to be read. the data byte which caused the overrun is lost.
rev. 0.2 179 c8051f336/7/8/9 23.5. serial clock phase and polarity four combinations of serial clock phase and polarity can be selected using the clock control bits in the spi0 configuration register (spi0c fg). the ckpha bit ( spi0cfg.5) selects one of two clock phases (edge used to latch the data). the ckpol bit (spi0cfg.4) selects between an active-high or active-low clock. both master and slave devices must be config ured to use the same clock phase and polarity. spi0 should be disabled (by clearing the spien bit, spi0 cn.0) when changing the clock phase or polarity. the clock and data line relationships for master mode are shown in figure 23.5 . for slave mode, the clock and data relationships are shown in figure 23.6 and figure 23.7 . note that ckpha must be set to ?0? on both the master and slave spi when communicating be tween two of the following devices: c8051f04x, c8051f06x, c8051f12x, c8051f31x, c8051f32x, and c8051f33x the spi0 clock rate register (spi0c kr) as shown in sfr definition 23.3 controls the master mode serial clock frequency. this register is ignored when operating in slave mode. when the spi is configured as a master, the maximum data transfer rate (bits/sec) is one-half the s ystem clock frequency or 12.5 mhz, whichever is slower. when the spi is configured as a sl ave, the maximum data transfer rate (bits/sec) for full-duplex operation is 1/10 the system clock frequency , provided that the master issues sck, nss (in 4- wire slave mode), and the serial input data synchrono usly with the slave?s system clock. if the master issues sck, nss, and the serial input data asynchronously, the maximum data transfer rate (bits/sec) must be less than 1/10 the system clock frequency. in the special case where the master only wants to transmit data to the slave and does not need to receive data from the slave (i.e. half-duplex operation), the spi slave can receive data at a maximum data transfer rate (bits/sec) of 1/4 the system clock frequency. this is provided that the master i ssues sck, nss, and the serial inpu t data synchronously with the slave?s system clock. sck (ckpol=0, ckpha=0) sck (ckpol=0, ckpha=1) sck (ckpol=1, ckpha=0) sck (ckpol=1, ckpha=1) msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 miso/mosi nss (must remain high in multi-master mode) figure 23.5. master mode data/clock timing
msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 miso nss (4-wire mode) msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mosi sck (ckpol=0, ckpha=0) sck (ckpol=1, ckpha=0) sck (ckpol=0, ckpha=1) sck (ckpol=1, ckpha=1) msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 miso nss (4-wire mode) msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mosi c8051f336/7/8/9 180 rev. 0.2 figure 23.6. slave mode data /clock timing (ckpha = 0) figure 23.7. slave mode data /clock timing (ckpha = 1) 23.6. spi special function registers spi0 is accessed and controlled through four special function registers in the system controller: spi0cn control register, spi0dat data re gister, spi0cfg configuration register, and spi0ckr clock rate register. the four special function registers related to the operation of the spi0 bus are described in the following figures.
sfr definition 23.1. spi0cfg: spi0 configuration bit 7 6 5 4 3 2 1 0 name type reset 0 0 0 0 0 1 1 1 rev. 0.2 181 c8051f336/7/8/9 sfr address = 0xa1 bit name function 7 spibsy spi busy. this bit is set to logic 1 when a spi transf er is in progress (master or slave mode). 6 msten master mode enable. 0: disable master mode. operate in slave mode. 1: enable master mode. operate as a master. 5 ckpha spi0 clock phase. 0: data centered on first edge of sck period. * 1: data centered on second edge of sck period. * 4 ckpol spi0 clock polarity. 0: sck line low in idle state. 1: sck line high in idle state. 3 slvsel slave selected flag. this bit is set to logic 1 whenever the nss pin is low indicating spi0 is the selected slave. it is cleared to logic 0 when nss is high (slave not sele cted). this bit does not indicate the instantaneous value at th e nss pin, but rather a de-glitched ver - sion of the pin input. 2 nssin nss instantaneous pin input. this bit mimics the instantaneous value that is present on the nss port pin at the time that the register is read. this input is not de-glitched. 1 srmt shift register empty (valid in slave mode only). this bit will be set to logic 1 when all data has been tran sferred in/out of the shift register, and there is no new information avai lable to read from the transmit buffer or write to the receive buffer . it returns to logic 0 when a data byte is transferred to the shift register from the transmit buffer or by a transition on sck. srmt = 1 when in master mode. 0 rxbmt receive buffer empty (valid in slave mode only). this bit will be set to logic 1 when the re ceive buffer has been read and contains no new information. if there is new informatio n available in the receive buffer that has not been read, this bit will return to logic 0. rxbmt = 1 when in master mode. *note: in slave mode, data on mosi is sampled in the center of each data bit. in master mode, data on miso is sampled one sysclk before the end of each data bit, to provide maximum settling time for the slave device. see table 23.1 for timing parameters. spibsy msten ckpha ckpol slvsel nssin srmt rxbmt r r/w r/w r/w r r r r
sfr definition 23.2. spi0cn: spi0 control bit 7 6 5 4 3 2 1 0 name spif wcol modf rxovrn nssmd[1:0] txbmt spien type r/w r/w r/w r/w r/w r r/w reset 0 0 0 0 0 1 1 0 c8051f336/7/8/9 182 rev. 0.2 sfr address = 0xf8; bit-addressable bit name function 7 spif spi0 interrupt flag. this bit is set to logic 1 by hardware at the end of a data transfer. if interrupts are enabled, setting this bit causes the cpu to vector to the spi0 interrupt service rou - tine. this bit is not automatically cleare d by hardware. it must be cleared by soft - ware. 6 wcol write collision flag. this bit is set to logic 1 by hardware (and generates a spi0 interrupt) to indicate a write to the spi0 data register was attempted while a data transfer was in progress. it must be cleared by software. 5 modf mode fault flag. this bit is set to logic 1 by hardware (and generates a spi0 interrupt) when a mas - ter mode collision is detected (nss is lo w, msten = 1, and nssmd[1:0] = 01). this bit is not automatically cleared by hardware. it must be cleared by software. 4 rxovrn receive overrun flag (valid in slave mode only). this bit is set to logic 1 by hardware (and generates a spi0 interrupt) when the receive buffer still holds unread data from a previous transf er and the last bit of the current transfer is shifted in to the spi0 shift register. th is bit is not automatically cleared by hardware. it must be cleared by software. 3:2 nssmd[1:0] slave select mode. selects between the following nss operation modes: (see section 23.2 and section 23.3). 00: 3-wire slave or 3-wire master mode. nss signal is not routed to a port pin. 01: 4-wire slave or multi-master mode (d efault). nss is an input to the device. 1x: 4-wire single-master mode. nss sign al is mapped as an output from the device and will assume the value of nssmd0. 1 txbmt transmit buffer empty. this bit will be set to logic 0 when new da ta has been written to the transmit buffer. when data in the transmit buff er is transferred to the spi shift register, this bit will be set to logic 1, indicating that it is safe to write a new byte to the transmit buffer. 0 spien spi0 enable. 0: spi disabled. 1: spi enabled.
sfr definition 23.3. spi0ckr: spi0 clock rate bit 7 6 5 4 3 2 1 0 name scr[7:0] type r/w reset 0 0 0 0 0 0 0 0 rev. 0.2 183 c8051f336/7/8/9 sfr address = 0xa2 bit name function 7:0 scr[7:0] spi0 clock rate. these bits determine the frequency of the sck output when the spi0 module is configured for master mode operation. the sck clock frequency is a divided ver - sion of the system clock, and is given in the following equation, where sysclk is the system clock frequency and spi0ckr is the 8-bit value held in the spi0ckr register. f sck sysclk 2 spi0ckr[7:0] 1 + () ------------------- ---------------------- ----------------- - = for 0 <= spi0ckr <= 255 example: if sysclk = 2 mhz and spi0ckr = 0x04, f sck 2000000 241 + () --------------- ----------- = f sck 200 khz = sfr definition 23.4. spi0dat: spi0 data bit 7 6 5 4 3 2 1 0 name spi0dat[7:0] type r/w reset 0 0 0 0 0 0 0 0 sfr address = 0xa3 bit name function 7:0 spi0dat[7:0] spi0 transmit and receive data. the spi0dat register is used to transmit and receive spi0 data. writing data to spi0dat places the data into the transmi t buffer and initiates a transfer when in master mode. a read of spi0dat returns the contents of the receive buffer.
sck* t mckh t mckl mosi t mis miso * sck is shown for ckpol = 0. sck is the opposite polarity for ckpol = 1. t mih sck* t mckh t mckl miso t mih mosi * sck is shown for ckpol = 0. sck is the opposite polarity for ckpol = 1. t mis c8051f336/7/8/9 184 rev. 0.2 figure 23.8. spi master timing (ckpha = 0) figure 23.9. spi master timing (ckpha = 1)
sck* t se nss t ckh t ckl mosi t sis t sih miso t sd t soh * sck is shown for ckpol = 0. sck is the opposite polarity for ckpol = 1. t sez t sdz sck* t se nss t ckh t ckl mosi t sis t sih miso t sd t soh * sck is shown for ckpol = 0. sck is the opposite polarity for ckpol = 1. t slh t sez t sdz rev. 0.2 185 c8051f336/7/8/9 figure 23.10. spi slave timing (ckpha = 0) figure 23.11. spi slave timing (ckpha = 1)
table 23.1. spi slave timing parameters parameter description min max units master mode timing * (see figure 23.8 and figure 23.9) t mckh sck high time 1 x t sysclk ? ns t mckl sck low time 1 x t sysclk ? ns t mis miso valid to sck shift edge 1 x t sysclk + 20 ? ns t mih sck shift edge to miso change 0 ? ns slave mode timing * (see figure 23.10 and figure 23.11) t se nss falling to first sck edge 2 x t sysclk ? ns t sd last sck edge to nss rising 2 x t sysclk ? ns t sez nss falling to miso valid ? 4 x t sysclk ns t sdz nss rising to miso high-z ? 4 x t sysclk ns t ckh sck high time 5 x t sysclk ? ns t ckl sck low time 5 x t sysclk ? ns t sis mosi valid to sck sample edge 2 x t sysclk ? ns t sih sck sample edge to mosi change 2 x t sysclk ? ns t soh sck shift edge to miso change ? 4 x t sysclk ns t slh last sck edge to miso change (ckpha = 1 only) 6 x t sysclk 8 x t sysclk ns *note: t sysclk is equal to one period of the device system clock (sysclk). c8051f336/7/8/9 186 rev. 0.2
rev. 0.2 187 c8051f336/7/8/9 24. timers each mcu includes four counter/timers: two are 16-bit counter/timers compatible with those found in the standard 8051, and two are 16-bit auto-reload timer fo r use with the adc, smbus, or for general purpose use. these timers can be used to measure time inte rvals, count external even ts and generate periodic interrupt requests. timer 0 and timer 1 are nearly identical and have four primary modes of operation. timer 2 and timer 3 offer 16-bit and split 8-bit timer function ality with auto-reload. additionally, timer 3 offers the ability to be clocked from the external oscillator while the dev ice is in suspend mode, and can be used as a wake-up source. this allows for implem entation of a very low-power system, including rtc capability. timers 0 and 1 may be clocked by one of five sources, determined by the timer mode select bits (t1m ? t0m) and the clock scale bits (sca1 ? sca0). the clock scale bits define a pre-scaled clock from which timer 0 and/or timer 1 may be clocked (see sfr definition 24.1 for pre-scaled cl ock selection). timer 0/1 may then be configured to use this pre-sc aled clock signal or th e system clock. timer 2 and timer 3 may be clocked by the system clock, the system clock divided by 12, or the external oscillator clock source divided by 8. timer 0 and timer 1 may also be operated as counters. when functioning as a counter, a counter/timer register is incremented on each high-to-low transition at the selected input pin (t0 or t1). events with a fre - quency of up to one-fourth the system clock frequen cy can be counted. the input signal need not be peri - odic, but it should be held at a gi ven level for at least two full system cl ock cycles to ensure the level is properly sampled. timer 0 and timer 1 modes: ti mer 2 modes: timer 3 modes: 13-bit counter/timer 16-bit timer with auto-reload 16-bit timer with auto-reload 16-bit counter/timer 8-bit counter/timer with auto- reload two 8-bit timers with auto-reload t wo 8-bit timers with auto-reload two 8-bit counter/timers (timer 0 only)
sfr definition 24.1. ckcon: clock control bit 7 6 5 4 3 2 1 0 name t3mh t3ml t2mh t2ml t1m t0m sca[1:0] type r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 c8051f336/7/8/9 188 rev. 0.2 sfr address = 0x8e bit name function 7 t3mh timer 3 high byte clock select. selects the clock supplied to the timer 3 high byte (split 8-bit timer mode only). 0: timer 3 high byte uses the clock defin ed by the t3xclk bit in tmr3cn. 1: timer 3 high byte uses the system clock. 6 t3ml timer 3 low byte clock select. selects the clock supplied to timer 3. selects the clock supplie d to the lower 8-bit timer in split 8-bit timer mode. 0: timer 3 low byte uses the clock defined by the t3xclk bit in tmr3cn. 1: timer 3 low byte uses the system clock. 5 t2mh timer 2 high byte clock select. selects the clock supplied to the timer 2 high byte (split 8-bit timer mode only). 0: timer 2 high byte uses the clock defin ed by the t2xclk bit in tmr2cn. 1: timer 2 high byte uses the system clock. 4 t2ml timer 2 low byte clock select. selects the clock supplied to timer 2. if timer 2 is configured in split 8-bit timer mode, this bit selects the clock supp lied to the lower 8-bit timer. 0: timer 2 low byte uses the clock defined by the t2xclk bit in tmr2cn. 1: timer 2 low byte uses the system clock. 3 t1 timer 1 clock select. selects the clock source supplied to timer 1. ignored when c/t1 is set to ?1?. 0: timer 1 uses the clock defined by the prescale bits sca[1:0]. 1: timer 1 uses the system clock. 2 t0 timer 0 clock select. selects the clock source supplied to timer 0. ignored when c/t0 is set to ?1?. 0: counter/timer 0 uses the clock defined by the prescale bits sca[1:0]. 1: counter/timer 0 uses the system clock. 1:0 sca[1:0] timer 0/1 prescale bits. these bits control the timer 0/1 clock prescaler: 00: system clock divided by 12 01: system clock divided by 4 10: system clock divided by 48 11: external clock divided by 8 (synchronized with the system clock)
rev. 0.2 189 c8051f336/7/8/9 24.1. timer 0 and timer 1 each timer is implemented as a 16-bit register acce ssed as two separate bytes: a low byte (tl0 or tl1) and a high byte (th0 or th1). the counter/timer co ntrol register (tcon) is used to enable timer 0 and timer 1 as well as indicate status. timer 0 interrupts can be enabled by setting the et0 bit in the ie regis - ter ( section ?15.2. interrupt register descriptions? on page 91 ); timer 1 interrupts can be enabled by set - ting the et1 bit in the ie register ( section ?15.2. interrupt register descriptions? on page 91 ). both counter/timers operate in one of four primary m odes selected by setting the mode select bits t1m1 ? t0m0 in the counter/timer mode register (tmod). each timer can be configured independently. each operating mode is described below. 24.1.1. mode 0: 13-bit counter/timer timer 0 and timer 1 operate as 13-bit counter/timers in mode 0. the following describes the configuration and operation of timer 0. however, both timers operate identically, and timer 1 is configured in the same manner as described for timer 0. the th0 register holds the eight msbs of the 13-bit c ounter/timer. tl0 holds the five lsbs in bit positions tl0.4 ? tl0.0. the three upper bits of tl0 (tl0.7 ? tl0.5) are indeterminate and should be masked out or ignored when reading. as the 13-bit timer register increments and overflows from 0x1fff (all ones) to 0x0000, the timer overflow flag tf0 (tcon.5) is set and an interr upt will occur if timer 0 interrupts are enabled. the c/t0 bit (tmod.2) selects the counter/time r's clock source. when c/t0 is set to logic 1, high-to-low transitions at the selected timer 0 input pin (t0) increment the timer register (refer to section ?20.3. priority crossbar decoder? on page 131 for information on selecting and configuring external i/o pins). clearing c/t selects the clock defined by the t0m bit (ckcon.3). when t0m is set, timer 0 is clocked by the system clock. when t0m is cleared, timer 0 is clocked by the source selected by the clock scale bits in ckcon (see sfr definition 24.1 ). setting the tr0 bit (tcon.4) enables the ti mer when either gate0 (tmod.3) is logic 0 or the input signal /int0 is active as defined by bit in0pl in register it01cf (see sfr definition 15.5 ). setting gate0 to ?1? allows the timer to be controlled by th e external input signal /int0 (see section ?15.2. interrupt register descriptions? on page 91 ), facilitating pulse width measurements note: x = don't care setting tr0 does not force the timer to reset. the timer registers should be loaded with the desired initial value before the timer is enabled. tl1 and th1 form the 13-bit register for timer 1 in the same manner as described above for tl0 and th0. timer 1 is configured and controlled using the releva nt tcon and tmod bits just as with timer 0. the input signal /int1 is used with timer 1; the /int1 polarity is defined by bit in1pl in register it01cf (see sfr definition 15.5 ). tr0 gate0 /int0 counter/timer 0 x x disabled 1 0 x enabled 1 1 0 disabled 1 1 1 enabled
tclk tl0 (5 bits) th0 (8 bits) tcon tf0 tr0 tr1 tf1 ie 1 it1 ie 0 it0 interrupt tr0 0 1 0 1 sysclk pre-scaled clock ckcon t 3 m h t 3 m l s c a 0 s c a 1 t 0 m t 2 m h t 2 m l t 1 m tmod t 1 m 1 t 1 m 0 c / t 1 g a t e 1 g a t e 0 c / t 0 t 0 m 1 t 0 m 0 gate0 /int0 t0 crossbar it01cf i n 1 s l 1 i n 1 s l 0 i n 1 s l 2 i n 1 p l i n 0 p l i n 0 s l 2 i n 0 s l 1 i n 0 s l 0 in 0pl xor c8051f336/7/8/9 190 rev. 0.2 figure 24.1. t0 mode 0 block diagram 24.1.2. mode 1: 16-bit counter/timer mode 1 operation is the same as mode 0, except that the counte r/timer registers use all 16 bits. the counter/timers are enabled and configured in mode 1 in the same manner as for mode 0.
rev. 0.2 191 c8051f336/7/8/9 24.1.3. mode 2: 8-bit counter/timer with auto-reload mode 2 configures timer 0 and timer 1 to operate as 8-bit counter/timers with automatic reload of the start value. tl0 holds the count and th0 holds the reload va lue. when the counter in tl0 overflows from all ones to 0x00, the timer over flow flag tf0 (tcon.5) is set and the co unter in tl0 is reloaded from th0. if timer 0 interrupts are enabled, an interr upt will occur when the tf0 flag is set. the reload value in th0 is not changed. tl0 must be initialized to the desired va lue before enabling the timer for the first count to be correct. when in mode 2, timer 1 operates identically to timer 0. both counter/timers are enabled and configured in mode 2 in the same manner as mode 0. setting the tr0 bit (tcon.4) enables the timer w hen either gate0 (tmod.3) is logic 0 or when the input signal /int0 is active as defined by bit in0pl in register it01cf (see section ?15.3. external interrupts /int0 and /int1? on page 96 for details on the external input signals /int0 and /int1). tclk tmod t 1 m 1 t 1 m 0 c / t 1 g a t e 1 g a t e 0 c / t 0 t 0 m 1 t 0 m 0 tcon tf0 tr0 tr1 tf1 ie1 it1 ie0 it0 interrupt tl0 (8 bits) reload th0 (8 bits) 0 1 0 1 sysclk pre-scaled clock it01cf i n 1 s l 1 i n 1 s l 0 i n 1 s l 2 i n 1 p l i n 0 p l i n 0 s l 2 i n 0 s l 1 i n 0 s l 0 tr0 gate0 in0pl xor /int0 t0 crossbar ckcon t 3 m h t 3 m l s c a 0 s c a 1 t 0 m t 2 m h t 2 m l t 1 m figure 24.2. t0 mode 2 block diagram
c8051f336/7/8/9 192 rev. 0.2 24.1.4. mode 3: two 8-bit counter/timers (timer 0 only) in mode 3, timer 0 is configured as two separate 8-bit co unter/timers held in tl0 and th0. the counter/timer in tl0 is controlled using the timer 0 control/status bits in tcon and tmod: tr0, c/t0, gate0 and tf0. tl0 can use either the system clock or an external input signal as its timebase. the th0 register is restricted to a timer function sourced by the system clock or prescaled clock. th0 is enabled using the timer 1 run control bit tr1. th0 sets the timer 1 overflow flag tf1 on overflow and thus controls the timer 1 interrupt. timer 1 is inactive in mode 3. when timer 0 is operating in mode 3, timer 1 can be operated in modes 0, 1 or 2, but cannot be clocked by external signals nor set the tf1 flag and generate an interrupt. however, the timer 1 overflow can be used to generate baud rates for the smbus and/or uart, and/or initiate adc conversions. while timer 0 is operating in mode 3, timer 1 run control is handled through its mode set - tings. to run timer 1 while timer 0 is in mode 3, set the timer 1 mode as 0, 1, or 2. to disable timer 1, configure it for mode 3. tl0 (8 bits) tmod 0 1 tcon tf0 tr0 tr1 tf1 ie1 it1 ie0 it0 interrupt interrupt 0 1 sysclk pre-scaled clock tr1 th0 (8 bits) t 1 m 1 t 1 m 0 c / t 1 g a t e 1 g a t e 0 c / t 0 t 0 m 1 t 0 m 0 tr0 gate0 in0pl xor /int0 t0 crossbar ckcon t 3 m h t 3 m l s c a 0 s c a 1 t 0 m t 2 m h t 2 m l t 1 m figure 24.3. t0 mode 3 block diagram
sfr definition 24.2. tcon: timer control bit 7 6 5 4 3 2 1 0 name type reset rev. 0.2 193 c8051f336/7/8/9 sfr address = 0x88; bit-addressable bit name function 7 tf1 timer 1 overflow flag. set to ?1? by hardware when timer 1 overflows. this flag can be cleared by software but is automatically cleared when the cpu vectors to the timer 1 interrupt service routine. 6 tr1 timer 1 run control. timer 1 is enabled by setting this bit to ?1?. 5 tf0 timer 0 overflow flag. set to ?1? by hardware when timer 0 overflows. this flag can be cleared by software but is automatically cleared when the cpu vectors to the timer 0 interrupt service routine. 4 tr0 timer 0 run control. timer 0 is enabled by setting this bit to ?1?. 3 ie1 external interrupt 1. this flag is set by hardware when an edge/l evel of type defined by it1 is detected. it can be cleared by software but is automatically cleared when the cpu vectors to the external interrupt 1 service routine in edge-triggered mode. 2 it1 interrupt 1 type select. this bit selects whether the configured /int 1 interrupt will be edge or level sensitive. /int1 is configured active low or high by the in1pl bit in the it01cf register (see sfr definition 15.5 ). 0: /int1 is level triggered. 1: /int1 is edge triggered. 1 ie0 external interrupt 0. this flag is set by hardware when an edge/l evel of type defined by it1 is detected. it can be cleared by software but is automatically cleared when the cpu vectors to the external interrupt 0 service routine in edge-triggered mode. 0 it0 interrupt 0 type select. this bit selects whether the configured /int 0 interrupt will be edge or level sensitive. /int0 is configured active low or high by the in0pl bit in register it01cf (see sfr definition 15.5 ). 0: /int0 is level triggered. 1: /int0 is edge triggered. tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 r/w r/w r/w r/w r/w r/w r/w r/w 00000000
sfr definition 24.3. tmod: timer mode bit 7 6 5 4 3 2 1 0 name type reset c8051f336/7/8/9 194 rev. 0.2 sfr address = 0x89 bit name function 7 gate1 timer 1 gate control. 0: timer 1 enabled when tr1 = 1 irrespective of /int1 logic level. 1: timer 1 enabled only when tr1 = 1 and /int1 is active as defined by bit in1pl in register it01cf (see sfr definition 15.5 ). 6 c/t1 counter/timer 1 select. 0: timer: timer 1 incremented by clock defined by t1m bit in register ckcon. 1: counter: timer 1 incremented by high-to-low transitions on external pin (t1). 5:4 t1m[1:0] timer 1 mode select. these bits select the timer 1 operation mode. 00: mode 0, 13-bit counter/timer 01: mode 1, 16-bit counter/timer 10: mode 2, 8-bit counter/timer with auto-reload 11: mode 3, timer 1 inactive 3 gate0 timer 0 gate control. 0: timer 0 enabled when tr0 = 1 irrespective of /int0 logic level. 1: timer 0 enabled only when tr0 = 1 and /int0 is active as defined by bit in0pl in register it01cf (see sfr definition 15.5 ). 2 c/t0 counter/timer 0 select. 0: timer: timer 0 incremented by clock defined by t0m bit in register ckcon. 1: counter: timer 0 incremented by high-to-low transitions on external pin (t0). 1:0 t0m[1:0] timer 0 mode select. these bits select the timer 0 operation mode. 00: mode 0, 13-bit counter/timer 01: mode 1, 16-bit counter/timer 10: mode 2, 8-bit counter/timer with auto-reload 11: mode 3, two 8-bit counter/timers gate1 c/t1 t1m[1:0] gate0 c/t0 t0m[1:0] r/w r/w r/w r/w r/w r/w 00000000
sfr definition 24.4. tl0: timer 0 low byte bit 7 6 5 4 3 2 1 0 name type reset rev. 0.2 195 c8051f336/7/8/9 sfr address = 0x8a bit name function 7:0 tl0[7:0] timer 0 low byte. the tl0 register is the low byte of the 16-bit timer 0. sfr definition 24.5. tl1: timer 1 low byte bit 7 6 5 4 3 2 1 0 name type reset sfr address = 0x8b bit name function 7:0 tl1[7:0] timer 1 low byte. the tl1 register is the low byte of the 16-bit timer 1. tl0[7:0] r/w 00000000 tl1[7:0] r/w 00000000
sfr definition 24.6. th0: timer 0 high byte bit 7 6 5 4 3 2 1 0 name type reset c8051f336/7/8/9 196 rev. 0.2 sfr address = 0x8c bit name function 7:0 th0[7:0] timer 0 high byte. the th0 register is the high byte of the 16-bit timer 0. sfr definition 24.7. th1: timer 1 high byte bit 7 6 5 4 3 2 1 0 name type reset sfr address = 0x8d bit name function 7:0 th1[7:0] timer 1 high byte. the th1 register is the high byte of the 16-bit timer 1. th0[7:0] r/w 00000000 th1[7:0] r/w 00000000
rev. 0.2 197 c8051f336/7/8/9 24.2. timer 2 timer 2 is a 16-bit timer formed by two 8-bit sfrs: tmr2l (low byte) and tmr2h (high byte). timer 2 may operate in 16-bit auto-reload mode or (split) 8-bit auto-reload mode. the t2split bit (tmr2cn.3) defines the timer 2 operation mode. timer 2 may be clocked by the system clock, the system clock divided by 12, or the external oscillator source divided by 8. the external clock mode is ideal for real-time clock (rtc) functionality, where the internal oscillator drives t he system clock while timer 2 (and/or the pca) is clocked by an external preci - sion oscillator. note that the external oscillator source divided by 8 is synchronized with the system clock. 24.2.1. 16-bit timer with auto-reload when t2split (tmr2cn. 3) is zero, timer 2 operates as a 16-bit time r with auto-reload. timer 2 can be clocked by sysclk, sysclk divided by 12, or the exte rnal oscillator clock source divided by 8. as the 16-bit timer register increments and overflows from 0xffff to 0x0000, the 16 -bit value in the timer 2 reload registers (tmr2rlh and tmr2rll) is loaded into the timer 2 register as shown in figure 24.4 , and the timer 2 high byte overflow flag (tmr2cn.7) is set. if timer 2 interrupts are enabled (if ie.5 is set), an interrupt will be gen erated on each timer 2 overflow. additionally, if timer 2 interrupts are enabled and the tf2len bit is set (tmr2cn. 5), an interr upt will be generated each time the lower 8 bits (tmr2l) overflow from 0xff to 0x00. external clock / 8 sysclk / 12 sysclk tmr2l tmr2h tmr2rll tmr2rlh reload tclk 0 1 tr2 tmr2cn t2split tf2cen tf2l tf2h t2xclk tr2 0 1 t2xclk interrupt tf2len to adc, smbus to smbus tl2 overflow ckcon t 3 m h t 3 m l s c a 0 s c a 1 t 0 m t 2 m h t 2 m l t 1 m figure 24.4. timer 2 16-bi t mode block diagram
c8051f336/7/8/9 198 rev. 0.2 24.2.2. 8-bit timers with auto-reload when t2split is set, timer 2 operates as two 8-bit timers (tmr2h and tmr2l). both 8-bit timers oper - ate in auto-reload mode as shown in figure 24.5 . tmr2rll holds the reload value for tmr2l; tmr2rlh holds the reload value for tmr2h. the tr2 bit in tmr2cn handles the run control for tmr2h. tmr2l is always running when configured for 8-bit mode. each 8-bit timer may be c onfigured to use sysclk, sysclk divided by 12, or the external oscillator clock source divided by 8. the timer 2 clock select bits (t2mh and t2ml in ckcon) select either sysclk or the clock defined by the timer 2 external clock select bit (t 2xclk in tmr2cn), as follows: the tf2h bit is set when tmr2h overflows from 0xff to 0x00; the tf2l bit is set when tmr2l overflows from 0xff to 0x00. when timer 2 interrupts are enabled (ie.5), an interrupt is generated each time tmr2h overflows. if timer 2 interrupts are enabled and tf2len (tmr2cn.5) is set, an interrupt is gener - ated each time either tmr2l or tmr2h overflows. when tf2len is enabled, software must check the tf2h and tf2l flags to determine the source of the timer 2 interrupt. the tf2h and tf2l interrupt flags are not cleared by hardware and must be manually cleared by software. sysclk tclk 0 1 tr2 external clock / 8 sysclk / 12 0 1 t2xclk 1 0 tmr2h tmr2rlh reload reload tclk tmr2l tmr2rll interrupt tmr2cn t2split tf2cen tf2len tf2l tf2h t2xclk tr2 to adc, smbus to smbus ckcon t 3 m h t 3 m l s c a 0 s c a 1 t 0 m t 2 m h t 2 m l t 1 m figure 24.5. timer 2 8- bit mode block diagram t2mh t2xclk tmr2h clock source t2ml t2xclk tmr2l clock source 0 0 sysclk / 12 0 0 sysclk / 12 0 1 external clock / 8 0 1 external clock / 8 1 x sysclk 1 x sysclk
rev. 0.2 199 c8051f336/7/8/9 24.2.3. low-frequency oscillator (lfo) capture mode the low-frequency oscillator capture mode allows the lfo clock to be measured against the system clock or an external oscillator source. timer 2 can be clocked from the system clock, the system clock divided by 12, or the external oscillator divided by 8, depending on the t2ml (ckcon.4), and t2xclk settings. setting tf2cen to ?1? enables the lfo capture mode for timer 2. in this mode, t2split should be set to ?0?, as the full 16-bit timer is used. upon a falling edge of the low-frequen cy oscillator, the contents of timer 2 (tmr2h:tmr2l) are loaded into the timer 2 reload registers (tmr2rlh :tmr2rll) and the tf2h flag is set. by recording the difference between two su ccessive timer capture valu es, the lfo clock frequency can be determined with respect to the timer 2 clock. the timer 2 clock should be much faster than the lfo to achieve an accurate reading. external clock / 8 sysclk / 12 sysclk 0 1 0 1 t2xclk ckcon t 3 m h t 3 m l s c a 0 s c a 1 t 0 m t 2 m h t 2 m l t 1 m tmr2l tmr2h tclk tr2 tmr2rll tmr2rlh capture low-frequency oscillator tmr2cn t2split tf2cen tf2l tf2h t2xclk tr2 tf2len tf2cen interrupt figure 24.6. timer 2 low-frequency osci llation capture mode block diagram
sfr definition 24.8. tmr2cn: timer 2 control bit 7 6 5 4 3 2 1 0 name tf2h tf2l tf2len tf2cen t2split tr2 t2xclk type reset c8051f336/7/8/9 200 rev. 0.2 sfr address = 0xc8; bit-addressable bit name function 7 tf2h timer 2 high byte overflow flag. set by hardware when the timer 2 high byte overflows from 0xff to 0x00. in 16 bit mode, this will occur when timer 2 overflows from 0xffff to 0x0000. when the timer 2 interrupt is enabled, setting this bit causes the cpu to vector to the timer 2 interrupt service routine. this bit is not automatically cleared by hardware. 6 tf2l timer 2 low byte overflow flag. set by hardware when the timer 2 low byte overflows from 0xff to 0x00. tf2l will be set when the low byte overflows regardless of the timer 2 mode. this bit is not automatically cleared by hardware. 5 tf2len timer 2 low byte interrupt enable. when set to ?1?, this bit enables timer 2 low byte interrupts. if timer 2 interrupts are also enabled, an interrupt will be ge nerated when the lo w byte of timer 2 overflows. 4 tf2cen timer 2 low-frequency oscillator capture enable. when set to ?1?, this bit enables timer 2 low-frequency oscilla tor capture mode. if tf2cen is set and timer 2 interrupts are enabled, an interrupt will be generated on a falling edge of the low-frequ ency oscillator output, an d the current 16-bit timer value in tmr2h:tmr2l will be copied to tmr2rlh:tmr2rll. 3 t2split timer 2 split mode enable. when this bit is set, timer 2 operates as two 8-bit timers with auto-reload. 0: timer 2 operates in 16-bit auto-reload mode. 1: timer 2 operates as two 8-bi t auto-reload timers. 2 tr2 timer 2 run control. timer 2 is enabled by setting this bit to ?1?. in 8-bit mode, this bit enables/disables tmr2h only; tmr2l is alwa ys enabled in split mode. 1 unused unused. read = 0b; write = don?t care 0 t2xclk timer 2 external clock select. this bit selects the external clock source for timer 2. if timer 2 is in 8-bit mode, this bit selects the external oscillator clock so urce for both timer bytes. however, the timer 2 clock select bits (t2mh and t2ml in register ckcon) may still be used to select between the external clock an d the system clock for either timer. 0: timer 2 clock is the system clock divided by 12. 1: timer 2 clock is the external clock divi ded by 8 (synchro nized with sysclk). r/w r/w r/w r/w r/w r/w r r/w 00000000
sfr definition 24.9. tmr2rll: timer 2 relo ad register low byte bit 7 6 5 4 3 2 1 0 name tmr2rll[7:0] type reset rev. 0.2 201 c8051f336/7/8/9 sfr address = 0xca bit name function 7:0 tmr2rll[7:0] timer 2 reload register low byte. tmr2rll holds the low byte of the reload value for timer 2. sfr definition 24.10. tmr2rlh: timer 2 relo ad register high byte bit 7 6 5 4 3 2 1 0 name tmr2rlh[7:0] type reset sfr address = 0xcb bit name function 7:0 tmr2rlh[7:0] timer 2 reload register high byte. tmr2rlh holds the high byte of the reload value for timer 2. sfr definition 24.11. tmr2l: timer 2 low byte bit 7 6 5 4 3 2 1 0 name tmr2l[7:0] type reset sfr address = 0xcc bit name function 7:0 tmr2l[7:0] timer 2 low byte. in 16-bit mode, the tmr2l register contains the low byte of the 16-bit timer 2. in 8- bit mode, tmr2l contains the 8-bit low byte timer value. r/w 00000000 r/w 00000000 r/w 00000000
sfr definition 24.12. tmr2h timer 2 high byte bit 7 6 5 4 3 2 1 0 name tmr2h[7:0] type reset c8051f336/7/8/9 202 rev. 0.2 sfr address = 0xcd bit name function 7:0 tmr2h[7:0] timer 2 low byte. in 16-bit mode, the tmr2h register contains the high byte of the 16-bit timer 2. in 8- bit mode, tmr2h contains the 8-bit high byte timer value. r/w 00000000
rev. 0.2 203 c8051f336/7/8/9 24.3. timer 3 timer 3 is a 16-bit timer formed by two 8-bit sfrs: tmr3l (low byte) and tmr3h (high byte). timer 3 may operate in 16-bit auto-reload mode or (split) 8-bit auto-reload mode. the t3split bit (tmr3cn.3) defines the timer 3 operation mode. timer 3 may be clocked by the system clock, the syste m clock divided by 12, the external oscillator source divided by 8, or the internal low-fr equency oscillator divided by 8. the ex ternal clock mode is ideal for real- time clock (rtc) functionality, wher e the internal high-frequency oscilla tor drives the system clock while timer 3 is clocked by an external oscillator source. note that the external oscillato r source divided by 8 and the lfo source divided by 8 are synchronized with the system clock when in all operating modes except suspend. when the internal oscillator is placed in suspend mode, the external clock / 8 signal or the lfo / 8 output can directly drive the timer. this allows the use of an external clock or the lfo to wake up the device from suspend mode. the time r will continue to run in suspend mo de and count up. when the timer overflow occurs, the device will wake from suspen d mode, and begin executing code again. the timer value may be set prior to entering suspend, to overflow in the desired amount of time (number of clocks) to wake the device. if a wake-up source other than t he timer wakes the device from suspend mode, it may take up to three timer clocks before the timer regist ers can be read or written. during this time, the stsync bit in register oscicn will be set to '1', to indica te that it is not safe to read or write the timer reg - isters. important note: in internal lfo / 8 mode, the divider for the internal lfo must be set to 1 for proper functionality. the timer will not operate if the lfo divider is not set to 1. 24.3.1. 16-bit timer with auto-reload when t3split (tmr3cn.3) is zero, timer 3 operates as a 16-bit timer with auto-reload. timer 3 can be clocked by sysclk, sysclk divided by 12, or the exte rnal oscillator clock source divided by 8. as the 16-bit timer register increments and overflows from 0xffff to 0x0000, the 16-bit value in the timer 3 reload registers (tmr3rlh and tmr3rll) is load ed into the timer 3 register as shown in figure 24.7 , and the timer 3 high byte overflow flag (tmr3cn.7) is set. if timer 3 interrupts are enabled (if eie1.7 is set), an interrupt will be generat ed on each timer 3 overflow. additiona lly, if timer 3 inte rrupts are enabled and the tf3len bit is set (tmr3cn. 5), an interr upt will be generated each time the lower 8 bits (tmr3l) overflow from 0xff to 0x00. sysclk tmr3l tmr3h tmr3rll tmr3rlh reload tclk 0 1 tr3 tmr3cn t3split t3xclk1 tf3cen tf3l tf3h t3xclk0 tr3 interrupt tf3len to adc ckcon t 3 m h t 3 m l s c a 0 s c a 1 t 0 m t 2 m h t 2 m l t 1 m external clock / 8 sysclk / 12 00 t3xclk[1:0] 01 11 internal lfo / 8 figure 24.7. timer 3 16-bi t mode block diagram
c8051f336/7/8/9 204 rev. 0.2 24.3.2. 8-bit timers with auto-reload when t3split is set, timer 3 operates as two 8-bi t timers (tmr3h and tmr3l). both 8-bit timers oper - ate in auto-reload mode as shown in figure 24.8 . tmr3rll holds the reload value for tmr3l; tmr3rlh holds the reload value for tmr3h. the tr3 bit in tmr3cn handles the run control for tmr3h. tmr3l is always running when configured for 8-bit mode. each 8-bit timer may be configured to use sysclk, sysc lk divided by 12, the external oscillator clock source divided by 8, or the intern al low-frequency oscilla tor. the timer 3 clock select bits (t3mh and t3ml in ckcon) select either sy sclk or the clock defined by the timer 3 external clock select bits (t3xclk[1:0] in tmr3cn), as follows: the tf3h bit is set when tmr3h overflows from 0xff to 0x00; the tf3l bit is set when tmr3l overflows from 0xff to 0x00. when timer 3 interrupts are enabled, an interrupt is generated each time tmr3h over - flows. if timer 3 interrupts are enabled and tf3len (tmr3cn.5) is set, an interrupt is generated each time either tmr3l or tmr3h overflows. when tf3le n is enabled, software must check the tf3h and tf3l flags to determine the source of the timer 3 interrupt. the tf3h and tf3l interrupt flags are not cleared by hardware and must be manually cleared by software. sysclk tclk 0 1 tr3 1 0 tmr3h tmr3rlh reload reload tclk tmr3l tmr3rll interrupt tmr3cn t3split t3xclk1 tf3cen tf3len tf3l tf3h t3xclk0 tr3 to adc external clock / 8 sysclk / 12 00 t3xclk[1:0] 01 11 internal lfo / 8 ckcon t 3 m h t 3 m l s c a 0 s c a 1 t 0 m t 2 m h t 2 m l t 1 m figure 24.8. timer 3 8- bit mode block diagram t3mh t3xclk[1:0] tmr3h clock source t3ml t3xclk[1:0] tmr3l clock source 0 00 sysclk / 12 0 00 sysclk / 12 0 01 external clock / 8 0 01 external clock / 8 0 10 reserved 0 10 reserved 0 11 internal lfo 0 11 internal lfo 1 x sysclk 1 x sysclk
rev. 0.2 205 c8051f336/7/8/9 24.3.3. low-frequency oscillator (lfo) capture mode the low-frequency oscillator capture mode allows the lfo clock to be measured against the system clock or an external oscillator source. timer 3 can be clocked from the system clock, the system clock divided by 12, or the external oscillator divide d by 8, depending on th e t3ml (ckcon.6), and t3xclk[1:0] settings. setting tf3cen to ?1? enables the lfo capture mode for timer 3. in this mode, t3split should be set to ?0?, as the full 16-bit timer is used . upon a falling edge of the low-frequency oscilla tor, the contents of timer 3 (tmr3h:tmr3l) are loaded into the timer 3 reload registers (tmr 3rlh:tmr3rll) and the tf3h flag is set. by recording the difference betw een two successive timer capture values, the lfo clock frequency can be determined with respect to the timer 3 clock. the timer 3 clock should be much faster than the lfo to achieve an accurate reading. this means that the lfo / 8 should not be selected as the timer clock source in this mode. external clock / 8 sysclk / 12 sysclk 0 1 00 01 t3xclk[1:0] ckcon t 3 m h t 3 m l s c a 0 s c a 1 t 0 m t 2 m h t 2 m l t 1 m tmr3l tmr3h tclk tr3 tmr3rll tmr3rlh capture low-frequency oscillator tmr3cn t3split t3xclk1 tf3cen tf3l tf3h t3xclk0 tr3 tf3len tf3cen interrupt figure 24.9. timer 3 low-frequency osci llation capture mode block diagram
sfr definition 24.13. tmr3cn: timer 3 control bit 7 6 5 4 3 2 1 0 name tf3h tf3l tf3len tf3cen t3split tr3 t3xclk[1:0] type reset c8051f336/7/8/9 206 rev. 0.2 sfr address = 0x91 bit name function 7 tf3h timer 3 high byte overflow flag. set by hardware when the timer 3 high byte overflows from 0xff to 0x00. in 16 bit mode, this will occur when timer 3 overflows from 0xffff to 0x0000. when the timer 3 interrupt is enabled, setting this bit causes the cpu to vector to the timer 3 interrupt service routine. this bit is not automatically cleared by hardware. 6 tf3l timer 3 low byte overflow flag. set by hardware when the timer 3 low byte overflows from 0xff to 0x00. tf3l will be set when the low byte overflows regardless of the timer 3 mode. this bit is not automatically cleared by hardware. 5 tf3len timer 3 low byte interrupt enable. when set to ?1?, this bit enables timer 3 low byte interrupts. if timer 3 interrupts are also enabled, an interrupt will be ge nerated when the lo w byte of timer 3 overflows. 4 tf3cen timer 3 low-frequency oscillator capture enable. when set to ?1?, this bit enables timer 3 low-frequency oscillator capture mode. if tf3cen is set and timer 3 interrupts are enabled, an interrupt will be generated on a falling edge of the low-frequ ency oscillator output, an d the current 16-bit timer value in tmr3h:tmr3l will be copied to tmr3rlh:tmr3rll. 3 t3split timer 3 split mode enable. when this bit is set, timer 3 operates as two 8-bit timers with auto-reload. 0: timer 3 operates in 16-bit auto-reload mode. 1: timer 3 operates as two 8-bi t auto-reload timers. 2 tr3 timer 3 run control. timer 3 is enabled by setting this bit to ?1?. in 8-bit mode, this bit enables/disables tmr3h only; tmr3l is alwa ys enabled in split mode. 1:0 t3xclk[1:0] timer 3 external clock select. this bit selects the ?external? clock source for timer 3. if timer 3 is in 8-bit mode, this bit selects the external oscillator clock source for both timer bytes. however, the timer 3 clock select bits (t3mh and t3ml in register ckcon) may still be used to select between the external clock an d the system clock for either timer. 00: system clock divided by 12. 01: external cl ock divided by 8 (synchronized with sysclk when not in suspend). 10: reserved. 11: internal lfo / 8 (synchronized with sysclk when not in suspend). r/w r/w r/w r/w r/w r/w r/w 00000000
sfr definition 24.14. tmr3rll: timer 3 relo ad register low byte bit 7 6 5 4 3 2 1 0 name tmr3rll[7:0] type reset rev. 0.2 207 c8051f336/7/8/9 sfr address = 0x92 bit name function 7:0 tmr3rll[7:0] timer 3 reload register low byte. tmr3rll holds the low byte of the reload value for timer 3. sfr definition 24.15. tmr3rlh: timer 3 relo ad register high byte bit 7 6 5 4 3 2 1 0 name tmr3rlh[7:0] type reset sfr address = 0x93 bit name function 7:0 tmr3rlh[7:0] timer 3 reload register high byte. tmr3rlh holds the high byte of the reload value for timer 3. sfr definition 24.16. tmr3l: timer 3 low byte bit 7 6 5 4 3 2 1 0 name tmr3l[7:0] type reset sfr address = 0x94 bit name function 7:0 tmr3l[7:0] timer 3 low byte. in 16-bit mode, the tmr3l register contains the low byte of the 16-bit timer 3. in 8-bit mode, tmr3l contains the 8-bit low byte timer value. r/w 00000000 r/w 00000000 r/w 00000000
sfr definition 24.17. tmr3h timer 3 high byte bit 7 6 5 4 3 2 1 0 name tmr3h[7:0] type reset c8051f336/7/8/9 208 rev. 0.2 sfr address = 0x95 bit name function 7:0 tmr3h[7:0] timer 3 high byte. in 16-bit mode, the tmr3h register contains the high byte of the 16-bit timer 3. in 8-bit mode, tmr3h contains the 8-bit high byte timer value. r/w 00000000
rev. 0.2 209 c8051f336/7/8/9 25. programmable counter array the programmable counter array (pca0) provides enhanced timer functionality while requiring less cpu intervention than the standard 8051 counter/timers. th e pca consists of a dedicated 16-bit counter/timer and three 16-bit capture/compare modules. each capt ure/compare module has its own associated i/o line (cexn) which is routed through the crossbar to port i/o when enabled. the counter/timer is driven by a programmable timebase that can select between six sources: system clo ck, system clock divided by four, system clock divided by twelve, the external oscillator cl ock source divided by 8, timer 0 overflows, or an external clock signal on the eci input pin. each capture/compare module may be configured to operate independently in one of six modes: edge-triggered capture, software timer, high-speed output, fre - quency output, 8 to 11-bit pwm, or 16 -bit pwm (each mode is described in section ?25.3. capture/compare modules? on page 212 ). the external oscillator clock option is ideal for real-time clock (rtc) functionality, allowing the pca to be clocke d by a precision external oscillator while the inter - nal oscillator drives the system clock. the pca is co nfigured and controlled thr ough the system controller's special function registers. the pca block diagram is shown in figure 25.1 important note: the pca module 2 may be used as a watchdog timer (wdt), and is enabled in this mode following a system reset. access to certain pca registers is restricted while wdt mode is enabled . see section 25.4 for details. capture/compare module 1 capture/compare module 0 capture/compare module 2 / wdt cex1 eci crossbar cex2 cex0 port i/o 16-bit counter/timer pca clock mux sysclk/12 sysclk/4 timer 0 overflow eci sysclk external clock/8 figure 25.1. pca block diagram
c8051f336/7/8/9 210 rev. 0.2 25.1. pca counter/timer the 16-bit pca counter/timer consists of two 8-bi t sfrs: pca0l and pca0h. pca0h is the high byte (msb) of the 16-bit counter/timer and pca0l is the lo w byte (lsb). reading pc a0l automatically latches the value of pca0h into a ?snapshot? register; the following pca0h read accesses this ?snapshot? register. reading the pca0l register first guarantees an accu rate reading of the entire 16-bit pca0 counter. reading pca0h or pca0l does not disturb the counter operation. the cps2 ? cps0 bits in the pca0md register select the timebase for the counter/timer as shown in ta b l e 25.1 . when the counter/timer overflows from 0xffff to 0x0 000, the counter overflow fl ag (cf) in pca0md is set to logic 1 and an interrupt request is generated if cf interrupts are enabled. setting the ecf bit in pca0md to logic 1 enables the cf flag to generate an interrupt request. the cf bit is not automatically cleared by hardware when the cpu vectors to the in terrupt service routine, and must be cleared by soft - ware. clearing the cidl bit in the pca0md register a llows the pca to continue normal operation while the cpu is in idle mode. table 25.1. pca timebase input options *note: external oscillator source divided by 8 is synchr onized with the system clock. pca0cn c f c r c c f 0 c c f 2 c c f 1 pca0md c i d l w d t e e c f c p s 1 c p s 0 w d l c k c p s 2 idle 0 1 pca0h pca0l snapshot register to sfr bus overflow to pca interrupt system cf pca0l read to pca modules sysclk/12 sysclk/4 timer 0 overflow eci 000 001 010 011 100 101 sysclk external clock/8 figure 25.2. pca counter /timer block diagram cps2 cps1 cps0 timebase 0 0 0 system clock divided by 12 0 0 1 system clock divided by 4 0 1 0 timer 0 overflow 011 high-to-low transitions on eci (max rate = system clock divided by 4) 1 0 0 system clock 101 external oscillator s ource divided by 8 * 1 1 x reserved
rev. 0.2 211 c8051f336/7/8/9 25.2. pca0 interrupt sources figure 25.3 shows a diagram of the pca interrupt tree. there are five independent event flags that can be used to generate a pca0 interrupt. they are: the main pca counter overflow flag (cf), which is set upon a 16-bit overflow of the pca0 counter, an intermediat e overflow flag (covf), which can be set on an over - flow from the 8th, 9th, 10th, or 11th bit of the pca0 counter, and the individual flags for each pca channel (ccf0, ccf1, and ccf2), which are set according to the operation mode of that module. these event flags are always set when the trigger condition occurs. ea ch of these flags can be individually selected to generate a pca0 interrupt, using the corresponding interrupt enable flag (ecf for cf, ecov for covf, and eccfn for each ccfn). pca0 interrupts must be globally enabled before any individual interrupt sources are recognized by the processor. pca0 interr upts are globally enabled by setting the ea bit and the epca0 bit to logic 1. pca0cn c f c r c c f 0 c c f 2 c c f 1 pca0md c i d l w d t e e c f c p s 1 c p s 0 w d l c k c p s 2 0 1 pca module 0 (ccf0) pca module 1 (ccf1) eccf1 0 1 eccf0 0 1 pca module 2 (ccf2) eccf2 pca counter/timer 16- bit overflow 0 1 interrupt priority decoder epca0 0 1 ea 0 1 pca0cpmn (for n = 0 to 2) p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n pca0pwm a r s e l c o v f c l s e l 0 c l s e l 1 e c o v pca counter/timer 8, 9, 10 or 11-bit overflow 0 1 set 8, 9, 10, or 11 bit operation figure 25.3. pca interrupt block diagram
c8051f336/7/8/9 212 rev. 0.2 25.3. capture/compare modules each module can be configured to operate independently in one of six operation modes: edge-triggered capture, software timer, high speed output, frequency output, 8 to 11-bit pulse width modulator, or 16- bit pulse width modulator. each module has special fu nction registers (sfrs) associated with it in the cip-51 system controller. these registers are used to exchange data with a module and configure the module's mode of operation. ta b l e 25.2 summarizes the bit settings in the pca0cpmn and pca0pwm registers used to select the pca capture/compare modu le?s operating mode. note that all modules set to use 8, 9, 10, or 11-bit pwm mode must use the same cycle length (8-11 bits). setting the eccfn bit in a pca0cpmn register enables the module's ccfn interrupt. table 25.2. pca0cpm and pca0pwm bit setti ngs for pca capture/compare modules notes: 1. x = don?t care (no functional difference for individual module if 1 or 0). 2. a = enable interrupts for this module (pca interrupt triggered on ccfn set to ?1?). 3. b = enable 8th, 9th, 10th or 11th bit overfl ow interrupt (depends on setting of clsel[1:0]). 4. c = when set to ?0?, the digital comparator is off. for high speed and frequency output modes, the associated pin will not toggle. in any of the pwm modes, this generates a 0% duty cycle (output = 0). 5. d = selects whether the capture/compare register (0) or the auto-reload register (1) for the associated channel is accessed via addresses pca0cphn and pca0cpln. 6. e = when set, a match event will cause the ccfn flag for the associated channel to be set. 7. all modules set to 8, 9, 10 or 11-bit pw m mode use the same cycle length setting. operational mode pca0cpmn pca0pwm bit number76543210765 4?2 1?0 capture triggered by positive edge on cexn xx10000a0xbxxx xx capture triggered by negative edge on cexn xx01000a0xbxxx xx capture triggered by any transition on cexn xx11000a0xbxxx xx software timer xc00100a0xbxxx xx high speed output xc00110a0xbxxx xx frequency output xc00011a0xbxxx xx 8-bit pulse width modulator (note 7) 0 c 0 0 e 0 1 a 0 x b xxx 00 9-bit pulse width modulator (note 7) 0 c 0 0 e 0 1 a d x b xxx 01 10-bit pulse width modulator (note 7) 0 c 0 0 e 0 1 a d x b xxx 10 11-bit pulse width modulator (note 7) 0 c 0 0 e 0 1 a d x b xxx 11 16-bit pulse width modulator 1 c 0 0 e 0 1 a 0 x b xxx xx
rev. 0.2 213 c8051f336/7/8/9 25.3.1. edge-triggered capture mode in this mode, a valid transition on the cexn pi n causes the pca to capture the value of the pca counter/timer and load it into the corresponding mo dule's 16-bit capture/compar e register (pca0cpln and pca0cphn). the cappn and capnn bits in the pca0cpmn register are used to select the type of transi - tion that triggers the capture: low-to-high transition (p ositive edge), high-to-low transition (negative edge), or either transition (positive or negative edge). when a capture occurs, the capture/compare flag (ccfn) in pca0cn is set to logic 1. an interrupt request is generated if the ccfn interrupt for that module is enabled. the ccfn bit is not automatically cleared by hardware when the cpu vectors to the interrupt ser - vice routine, and must be clea red by software. if bo th cappn and capnn bi ts are set to logic 1, then the state of the port pin associated wit h cexn can be read directly to de termine whether a rising-edge or fall - ing-edge caused the capture. pca0l pca0cpln pca timebase cexn crossbar port i/o pca0h capture pca0cphn 0 1 0 1 (to ccfn) pca0cpmn p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n pca0cn c f c r c c f 0 c c f 2 c c f 1 pca interrupt x000x x figure 25.4. pca capture mode diagram note: the cexn input signal must remain high or low for at least 2 system clock cycles to be recognized by the hardware.
c8051f336/7/8/9 214 rev. 0.2 25.3.2. software timer (compare) mode in software timer mode, the pca c ounter/timer value is compared to the module's 16-bit capture/compare register (pca0cphn and pca0cpln). when a match occurs, the capture/compare flag (ccfn) in pca0cn is set to logic 1. an interrupt request is generated if the ccfn interrupt for that module is enabled. the ccfn bit is not automatically cleared by hardware when the cpu vectors to the interrupt ser - vice routine, and must be cleared by software. setting the ecomn and matn bits in the pca0cpmn regis - ter enables software timer mode. important note about capture/compare registers : when writing a 16-bit value to the pca0 cap - ture/compare registers, the low byte should alwa ys be written first. writing to pca0cpln clears the ecomn bit to ?0?; writing to pca0cphn sets ecomn to ?1?. match 16-bit comparator pca0h pca0cphn enable pca0l pca timebase pca0cpln 00 00 0 1 x enb enb 0 1 write to pca0cpln write to pca0cphn reset pca0cpmn p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n x pca0cn c f c r c c f 0 c c f 2 c c f 1 pca interrupt figure 25.5. pca software timer mode diagram
rev. 0.2 215 c8051f336/7/8/9 25.3.3. high-speed output mode in high-speed output mode, a module?s associated cexn pin is toggled each time a match occurs between the pca counter and the module's 16- bit capture/compare register (pca0cphn and pca0cpln). when a match occurs, the capture/comp are flag (ccfn) in pca0cn is set to logic 1. an interrupt request is generated if the ccfn interrupt for that module is enabled. the ccfn bit is not auto - matically cleared by hardware when the cpu vectors to the interrupt service routine, and must be cleared by software. setting the togn, matn, and ecomn bi ts in the pca0cpmn register enables the high- speed output mode. if ecomn is cleare d, the associated pin will retain it s state, and not toggle on the next match event. important note about capture/compare registers : when writing a 16-bit value to the pca0 cap - ture/compare registers, the low byte should alwa ys be written first. writing to pca0cpln clears the ecomn bit to ?0?; writing to pca0cphn sets ecomn to ?1?. match 16-bit comparator pca0h pca0cphn enable pca0l pca timebase pca0cpln 0 1 00 0x enb enb 0 1 write to pca0cpln write to pca0cphn reset pca0cpmn p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n x cexn crossbar port i/o toggle 0 1 togn pca0cn c f c r c c f 0 c c f 2 c c f 1 pca interrupt figure 25.6. pca high-spee d output mode diagram
c8051f336/7/8/9 216 rev. 0.2 25.3.4. frequency output mode frequency output mode produces a programmable-freq uency square wave on the module?s associated cexn pin. the capture/compare module high byte holds the number of pca clocks to count before the out - put is toggled. the frequency of the square wave is then defined by equation 25.1 . f cexn f pca 2 pca 0 cphn ------------------- --------------------- - = note: a value of 0x00 in the pca0cphn re gister is equal to 256 for this equation. equation 25.1. square wave fr equency output where f pca is the frequency of the clock selected by the cps2 ? 0 bits in the pca mode register, pca0md. the lower byte of the capture/compare modu le is compared to the pca counter low byte; on a match, cexn is toggled and the offset held in the hi gh byte is added to the matched value in pca0cpln. frequency output mode is enabled by setting the ecomn, togn, and pwmn bits in the pca0cpmn reg - ister. note that the matn bit should no rmally be set to ?0? in this mode. if the matn bit is set to ?1?, the ccfn flag for the channel will be set when t he 16-bit pca0 counter and the 16-bit capture/compare register for the channel are equal. 8-bit comparator pca0l enable pca timebase match pca0cphn 8-bit adder pca0cpln adder enable cexn crossbar port i/o toggle 0 1 togn 000 x pca0cpmn p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n x enb enb 0 1 write to pca0cpln write to pca0cphn reset figure 25.7. pca frequency output mode
rev. 0.2 217 c8051f336/7/8/9 25.3.5. 8-bit, 9-bit, 10-bit and 11-bit pulse width modulator modes each module can be used independently to generate a pulse width modulated (pwm) output on its associ - ated cexn pin. the frequency of the output is depe ndent on the timebase for the pca counter/timer, and the setting of the pwm cycle length (8, 9, 10 or 11 -bits). for backwards-compa tibility with the 8-bit pwm mode available on other devices, the 8-bit pwm mode operates slightly differen t than 9, 10 and 11-bit pwm modes. it is important to note that all channels configured for 8/9/10/11-bit pwm mode will use the same cycle length. it is not possible to configure one channel for 8-bit pwm mode and another for 11- bit mode (for example). however, other pca channels can be configured to pin capture, high-speed out - put, software timer, frequency output, or 16-bit pwm mode independently. 25.3.5.1. 8-bit pulse width modulator mode the duty cycle of the pwm output signal in 8-bit pwm mode is varied using the module's pca0cpln cap - ture/compare register. when the value in the low byte of the pca counter/timer (pca0l) is equal to the value in pca0cpln, the output on th e cexn pin will be set. when the coun t value in pca0l overflows, the cexn output will be reset (see figure 25.8 ). also, when the counter/timer low byte (pca0l) overflows from 0xff to 0x00, pca0cpln is reloaded automatically with the value stored in the module?s capture/compare high byte (pca0cphn) without software intervention. setting the ecomn and pwmn bits in the pca0cpmn register, and setting the clsel bits in register pca0pwm to 00b enables 8-bit pulse width modulator mode. if the matn bit is se t to ?1?, the ccfn flag for the modu le will be set each time an 8-bit comparator match (rising edge) occurs. the covf flag in pca0pwm can be used to detect the overflow (falling edge), which will occur every 256 pca clock cyc les. the duty cycle for 8-bit pwm mode is given in equation 25.2 . important note about capture/compare registers : when writing a 16-bit value to the pca0 cap - ture/compare registers, the low byte should alwa ys be written first. writing to pca0cpln clears the ecomn bit to ?0?; writing to pca0cphn sets ecomn to ?1?. duty cycle 256 pca 0 cphn ? () 256 ------------------ ----------------- ---------------- = equation 25.2. 8-bit pwm duty cycle using equation 25.2, the largest duty cycle is 100% (pca0c phn = 0), and the smallest duty cycle is 0.39% (pca0cphn = 0xff). a 0% duty cycle may be generated by clearing the ecomn bit to ?0?.
8-bit comparator pca0l pca0cpln pca0cphn cexn crossbar port i/o enable overflow pca timebase 00x0 x q q set clr s r match pca0cpmn p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n 0 pca0pwm a r s e l c o v f c l s e l 0 c l s e l 1 e c o v x0 0 0 enb enb 0 1 write to pca0cpln write to pca0cphn reset covf c8051f336/7/8/9 218 rev. 0.2 figure 25.8. pca 8-bi t pwm mode diagram
rev. 0.2 219 c8051f336/7/8/9 25.3.5.2. 9/10/11-bit pulse width modulator mode the duty cycle of the pwm output signa l in 9/10/11-bit pwm mode should be varied by writing to an ?auto- reload? register, which is dual-mapped into the pc a0cphn and pca0cpln register locations. the data written to define the duty cycle should be right-just ified in the registers. the auto-reload registers are accessed (read or written) when the bit arsel in pca0pwm is set to ?1?. the capture/compare registers are accessed when arsel is set to ?0?. when the least-significant n bits of the pca0 coun ter match the value in the associated module?s cap - ture/compare register (pca0cpn), the output on cexn is asserted high. when the counter overflows from the nth bit, cexn is asserted low (see figure 1 ). upon an overflow from the nth bit, the covf flag is set, and the value stored in the module?s auto-reload regi ster is loaded into the capture/compare register. the value of n is determined by the clsel bits in register pca0pwm. the 9, 10 or 11-bit pwm mode is selected by setting the ecomn and pwmn bits in the pca0cpmn regis - ter, and setting the clsel bits in register pca0pwm to the desired cycle length (other than 8-bits). if the matn bit is set to ?1?, the ccfn fl ag for the module will be set each ti me a comparator match (rising edge) occurs. the covf flag in pca0pwm can be used to detect the overflow (f alling edge), which will occur every 512 (9-bit), 1024 (10-bit) or 2048 (11-bit) pca clock cycles . the duty cycle for 9/10/11-bit pwm mode is given in equation 25.2 , where n is the number of bits in the pwm cycle. important note about pca0cphn and pca0cpln registers : when writing a 16-bit value to the pca0cpn registers, the low byte should always be wr itten first. writing to pca0cpln clears the ecomn bit to ?0?; writing to pc a0cphn sets ecomn to ?1?. duty cycle 2 n pca 0 cpn ? () 2 n ------------------ -------------- ----------- - = equation 25.3. 9, 10, and 11-bit pwm duty cycle a 0% duty cycle may be generated by clearing the ecomn bit to ?0?. n-bit comparator pca0h:l (capture/compare) pca0cph:ln (right-justified) (auto-reload) pca0cph:ln (right-justified) cexn crossbar port i/o enable overflow of n th bit pca timebase 00x0 x q q set clr s r match pca0cpmn p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n 0 pca0pwm a r s e l c o v f c l s e l 0 c l s e l 1 e c o v x enb enb 0 1 write to pca0cpln write to pca0cphn reset r/w when arsel = 1 r/w when arsel = 0 set ?n? bits: 01 = 9 bits 10 = 10 bits 11 = 11 bits figure 1. pca 9, 10 and 11-bit pwm mode diagram
c8051f336/7/8/9 220 rev. 0.2 25.3.6. 16-bit pulse width modulator mode a pca module may also be operated in 16-bit pwm mode. 16-bit pwm mode is independent of the other (8/9/10/11-bit) pwm modes. in this mode, the 16-bit capture/compare module defines the number of pca clocks for the low time of the pwm signal. when the pca counter matches the module contents, the out - put on cexn is asserted high; when the 16-bit counte r overflows, cexn is asserted low. to output a vary - ing duty cycle, new value writes should be synchr onized with pca ccfn match interrupts. 16-bit pwm mode is enabled by setting the ecomn, pwmn, and pwm16n bits in the pca0cpmn register. for a vary - ing duty cycle, match interrupts should be enabled (eccfn = 1 and matn = 1) to help synchronize the capture/compar e register writes. if the matn bit is set to ?1 ?, the ccfn flag for the module will be set each time a 16-bit comparator match (rising edge) occurs. the cf flag in pca0cn can be used to detect the overflow (falling edge). the duty cycl e for 16-bit pwm mode is given by equation 25.4 . important note about capture/compare registers : when writing a 16-bit value to the pca0 cap - ture/compare registers, the low byte should alwa ys be written first. writing to pca0cpln clears the ecomn bit to ?0?; writing to pca0cphn sets ecomn to ?1?. duty cycle 65536 pca 0 cpn ? () 65536 ------------------ ------------------ ---------------- - = equation 25.4. 16-bit pwm duty cycle using equation 25.4, the largest duty cycle is 100% (pca0c pn = 0), and the smallest duty cycle is 0.0015% (pca0cpn = 0xffff). a 0% duty cycle may be generated by clearing the ecomn bit to ?0?. pca0cpln pca0cphn enable pca timebase 00x0 x pca0cpmn p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n 1 16-bit comparator cexn crossbar port i/o overflow q q set clr s r match pca0h pca0l enb enb 0 1 write to pca0cpln write to pca0cphn reset figure 25.9. pca 16-bit pwm mode
rev. 0.2 221 c8051f336/7/8/9 25.4. watchdog timer mode a programmable watchdog timer (wdt) function is avai lable through the pca module 2. the wdt is used to generate a reset if the time between writes to th e wdt update register (pca0cph2) exceed a specified limit. the wdt can be configured and enabled/disabled as needed by software. with the wdte bit set in the pca0md register, modu le 2 operates as a watchdog timer (wdt). the mod - ule 2 high byte is compared to the pca counter high byte; the module 2 low byte holds the offset to be used when wdt updates are performed. the watchdog timer is enabled on reset. writes to some pca registers are restricted while the watchdog timer is enabled. the wdt will generate a reset shortly after code begins execution. to avoid this re set, the wdt should be explicitly disabled (and option - ally re-configured and re-enabled if it is used in the system). 25.4.1. watchdog timer operation while the wdt is enabled: ? pca counter is forced on. ? writes to pca0l and pca0h are not allowed. ? pca clock source bits (cps2 ? cps0) are frozen. ? pca idle control bi t (cidl) is frozen. ? module 2 is forced in to software timer mode. ? writes to the module 2 mode register (pca0cpm2) are disabled. while the wdt is enabled, writes to the cr bit will not change the pca counter state; the counter will run until the wdt is disabled. the pca counter run control bit (cr) will re ad zero if the wdt is enabled but user software has not enabled th e pca counter. if a match occurs between pca0cph2 and pca0h while the wdt is enabled, a reset will be generated. to pr event a wdt reset, the wd t may be up dated with a write of any value to pca0cph2. up on a pca0cph2 write, pca0h plus the offset held in pca0cpl2 is loaded into pca0cph2 (see figure 25.10 ). pca0h enable pca0l overflow reset pca0cpl2 8-bit adder pca0cph2 adder enable pca0md c i d l w d t e e c f c p s 1 c p s 0 w d l c k c p s 2 match write to pca0cph2 8-bit comparator figure 25.10. pca module 2 wi th watchdog timer enabled
c8051f336/7/8/9 222 rev. 0.2 note that the 8-bit offset held in pca0cph2 is comp ared to the upper byte of the 16-bit pca counter. this offset value is the number of pca0l overflows before a reset. up to 256 pca clocks may pass before the first pca0l overflow occurs, depending on the valu e of the pca0l when the update is performed. the total offset is then given (in pca clocks) by equation 25.5 , where pca0l is the value of the pca0l register at the time of the update. offset 256 pca 0 cpl 2 () 256 pca 0 l ? () + = equation 25.5. watchdog timer offset in pca clocks the wdt reset is generated when pca0l overflow s while there is a match between pca0cph2 and pca0h. software may force a wdt reset by writing a ?1? to the ccf2 flag (pca0cn.2) while the wdt is enabled. 25.4.2. watchdog timer usage to configure the wdt, perform the following tasks: ? disable the wdt by writing a ?0? to the wdte bit. ? select the desired pca cl ock source (with the cps2 ? cps0 bits). ? load pca0cpl2 with the desi red wdt update offset value. ? configure the pca idle mode (set cidl if the wdt should be suspended while the cpu is in idle mode). ? enable the wdt by setting the wdte bit to ?1?. ? reset the wdt timer by writing to pca0cph2. the pca clock source and idle mode select cannot be changed while the wdt is enabled. the watchdog timer is enabled by setting the wdte or wdlck bits in the pca0md register. when wdlck is set, the wdt cannot be disabled until the next system reset. if wdlck is not set, the wdt is disabled by clearing the wdte bit. the wdt is enabled following any rese t. the pca0 counter clock defaults to the system clock divided by 12, pca0l defaults to 0x00, and pca0cpl2 defaults to 0x00. using equation 25.5 , this results in a wdt timeout interval of 256 pca clock cycles, or 3072 system clock cycles. ta b l e 25.3 lists some example tim - eout intervals for ty pical system clocks. table 25.3. watchdog timer timeout intervals 1 notes: 1. assumes sysclk/12 as the pca clock source, and a pca0l value of 0x00 at the update time. 2. internal sysclk reset frequency = internal oscillator divided by 8. system clock (hz) pca0cpl2 timeout interval (ms) 24,500,000 255 32.1 24,500,000 128 16.2 24,500,000 32 4.1 3,062,500 2 255 257 3,062,500 2 128 129.5 3,062,500 2 32 33.1 32,000 255 24576 32,000 128 12384 32,000 32 3168
rev. 0.2 223 c8051f336/7/8/9 25.5. register descriptions for pca0 following are detailed descriptions of the special func tion registers related to the operation of the pca. sfr definition 25.1. pca0cn: pca control bit 7 6 5 4 3 2 1 0 name cf cr ccf2 ccf1 ccf0 type r/w r/w r r r r/w r/w r/w reset 0 0 0 0 0 0 0 0 sfr address = 0xd8; bit-addressable bit name function 7 cf pca counter/timer overflow flag. set by hardware when the pca counter/timer overflows from 0xffff to 0x0000. when the counter/timer overflow (cf) interrupt is enabled, setting this bit causes the cpu to vector to the pca interrupt service r outine. this bit is not automatically cleared by hardware and must be cleared by software. 6 cr pca counter/timer run control. this bit enables/disables the pca counter/timer. 0: pca counter/timer disabled. 1: pca counter/timer enabled. 5:3 unused unused. read = 000b, write = don't care. 2 ccf2 pca module 2 capture/compare flag. this bit is set by hardware when a match or capture occurs. when the ccf2 interrupt is enabled, setting this bit causes the cpu to vector to the pca interrupt service rou - tine. this bit is not automatically cleared by hardware and must be cleared by software. 1 ccf1 pca module 1 capture/compare flag. this bit is set by hardware when a match or capture occurs. when the ccf1 interrupt is enabled, setting this bit causes the cpu to vector to the pca interrupt service rou - tine. this bit is not automatically cleared by hardware and must be cleared by software. 0 ccf0 pca module 0 capture/compare flag. this bit is set by hardware when a match or capture occurs. when the ccf0 interrupt is enabled, setting this bit causes the cpu to vector to the pca interrupt service rou - tine. this bit is not automatically cleared by hardware and must be cleared by software.
sfr definition 25.2. pca0md: pca mode bit 7 6 5 4 3 2 1 0 name cidl wdte wdlck cps2 cps1 cps0 ecf type r/w r/w r/w r r/w r/w r/w r/w reset 0 1 0 0 0 0 0 0 c8051f336/7/8/9 224 rev. 0.2 sfr address = 0xd9 bit name function 7 cidl pca counter/timer idle control. specifies pca behavior when cpu is in idle mode. 0: pca continues to function normally while the system co ntroller is in idle mode. 1: pca operation is suspended while th e system controller is in idle mode. 6 wdte watchdog timer enable if this bit is set, pca module 2 is used as the watchdog timer. 0: watchdog timer disabled. 1: pca module 2 enabled as watchdog timer. 5 wdlck watchdog timer lock this bit locks/unlocks the watchdog timer e nable. when wdlck is set, the watchdog timer may not be disabled until the next system reset. 0: watchdog timer enable unlocked. 1: watchdog timer enable locked. 4 unused unused. read = 0b, write = don't care. 3:1 cps[2:0] pca counter/timer pulse select. these bits select the timebase source for the pca counter 000: system clock divided by 12 001: system clock divided by 4 010: timer 0 overflow 011: high-to-low transitions on eci (max rate = system clock divided by 4) 100: system clock 101: external clock divided by 8 (synchronized with the system clock) 11x: reserved 0 ecf pca counter/timer overflow interrupt enable. this bit sets the masking of the pca co unter/timer overflow (cf) interrupt. 0: disable the cf interrupt. 1: enable a pca counter/timer overflow in terrupt request when cf (pca0cn.7) is set. note: when the wdte bit is set to ?1?, the other bits in the pca0md register cannot be modified. to change the contents of the pca0md register, the watchdog timer must first be disabled.
sfr definition 25.3. pca0pwm: pca pwm configuration bit 7 6 5 4 3 2 1 0 name arsel ecov covf clsel[1:0] type r/w r/w r/w r r r r/w reset 0 0 0 0 0 0 0 0 rev. 0.2 225 c8051f336/7/8/9 sfr address = 0xf7 bit name function 7 arsel auto-reload register select. this bit selects whether to read and write the normal pca capture/compare registers (pca0cpn), or the auto-reload registers at the same sfr addresses. this function is used to define the reload value for 9, 10, and 11-bit pwm modes. in all other modes, the auto-reload registers have no function. 0: read/write capture/compare registers at pca0cphn and pca0cpln. 1: read/write auto-reload regi sters at pca0cphn and pca0cpln. 6 ecov cycle overflow interrupt enable. this bit sets the masking of the cycle overflow flag (covf) interrupt. 0: covf will not gene rate pca interrupts. 1: a pca interrupt will be ge nerated when covf is set. 5 covf cycle overflow flag. this bit indicates an overflow of the 8th, 9th, 10th, or 11th bit of the main pca counter (pca0). the specific bit used for this flag depends on the setting of the cycle length select bits. the bit can be set by hardware or software, but must be cleared by soft - ware. 0: no overflow has occurred since the last time this bit was cleared. 1: an overflow has occurred since t he last time this bit was cleared. 4:2 unused unused. read = 000b; write = don?t care. 1:0 clsel[1:0] cycle length select. when 16-bit pwm mode is not selected, th ese bits select the length of the pwm cycle, between 8, 9, 10, or 11 bits. this affects all channels configured for pwm which are not using 16-bit pwm mode. these bits are ignored for individual channels config - ured to16-bit pwm mode. 00: 8 bits. 01: 9 bits. 10: 10 bits. 11: 11 bits.
sfr definition 25.4. pca0cpmn: pca capture/compare mode bit 7 6 5 4 3 2 1 0 name pwm16n ecomn cappn capnn matn togn pwmn eccfn type r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 c8051f336/7/8/9 226 rev. 0.2 sfr addresses: pca0cpm0 = 0xda , pca0cpm1 = 0xdb , pca0cpm2 = 0xdc bit name function 7 pwm16n 16-bit pulse width modulation enable. this bit enables 16-bit mode when pulse width modulation mode is enabled. 0: 8 to 11-bit pwm selected. 1: 16-bit pwm selected. 6 ecomn comparator function enable. this bit enables the comparator function for pca module n when set to ?1?. 5 cappn capture positive function enable. this bit enables the positive edge capture for pca module n when set to ?1?. 4 capnn capture negative function enable. this bit enables the negative edge capture for pca module n when set to ?1?. 3 matn match function enable. this bit enables the match function for pca module n when set to ?1?. when enabled, matches of the pca counter with a module's capture/compare regist er cause the ccfn bit in pca0md register to be set to logic 1. 2 togn toggle function enable. this bit enables the toggle function for pca module n when set to ?1?. when enabled, matches of the pca counter with a module's capture/compare register cause the logic level on the cexn pin to toggle . if the pwmn bit is also set to logic 1, the module oper - ates in frequency output mode. 1 pwmn pulse width modulation mode enable. this bit enables the pwm function for pca module n when set to ?1?. when enabled, a pulse width modulated signal is output on the cexn pin. 8 to 11-bit pwm is used if pwm16n is cleared; 16-bit mode is used if pwm1 6n is set to logic 1. if the togn bit is also set, the module operates in frequency output mode. 0 eccfn capture/compare flag interrupt enable. this bit sets the masking of the ca pture/compare flag (ccfn) interrupt. 0: disable ccfn interrupts. 1: enable a capture/compare flag interrupt request when ccfn is set. note: when the wdte bit is set to ?1?, the pca0cpm2 regist er cannot be modified, and module 2 acts as the watchdog timer. to change the contents of the pca0cpm2 register or the function of module 2, the watchdog timer must be disabled.
sfr definition 25.5. pca0l: pca counter/timer low byte bit 7 6 5 4 3 2 1 0 name pca0[7:0] type r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 rev. 0.2 227 c8051f336/7/8/9 sfr address = 0xf9 bit name function 7:0 pca0[7:0] pca counter/timer low byte. the pca0l register holds the low byte (lsb) of the 16-bit pca counter/timer. note: when the wdte bit is set to ?1?, the pca0l register cannot be modified by software. to change the contents of the pca0l register, the watchdog timer must first be disabled. sfr definition 25.6. pca0h: pca counter/timer high byte bit 7 6 5 4 3 2 1 0 name pca0[15:8] type r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 sfr address = 0xfa bit name function 7:0 pca0[15:8] pca counter/timer high byte. the pca0h register holds the high byte (msb) of the 16-bit pca counter/timer. reads of this register will re ad the contents of a ?snapshot ? register, whose contents are updated only when the cont ents of pca0l are read (see section 25.1 ). note: when the wdte bit is set to ?1?, t he pca0h register cannot be modified by software. to change the contents of the pca0h register, the watchdog timer must first be disabled.
sfr definition 25.7. pca0cpln: pca capt ure module low byte bit 7 6 5 4 3 2 1 0 name pca0cpn[7:0] type r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 c8051f336/7/8/9 228 rev. 0.2 sfr addresses: pca0cpl0 = 0xfb , pca0cpl1 = 0xe9 , pca0cpl2 = 0xeb bit name function 7:0 pca0cpn[7:0] pca capture module low byte. the pca0cpln register holds the low byte (lsb) of the 16-bit capture module n. this register address also allows acce ss to the low byte of the corresponding pca channel?s auto-reload value for 9, 10, or 11-bit pwm mode. the arsel bit in register pca0pwm controls which register is accessed. note: a write to this register will clear the module?s ecomn bit to a ?0?. sfr definition 25.8. pca0cphn: pca capture module high byte bit 7 6 5 4 3 2 1 0 name pca0cpn[15:8] type r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 sfr addresses: pca0cph0 = 0xfc , pca0cph1 = 0xea , pca0cph2 = 0xec bit name function 7:0 pca0cpn[15:8] pca capture module high byte. the pca0cphn register holds the high byte (msb) of the 16-bit capture module n. this register address also allows access to the high byte of the corresponding pca channel?s auto-reload value for 9, 10, or 11-bit pwm mode. the arsel bit in register pca0pwm controls which register is accessed. note: a write to this register will set the module?s ecomn bit to a ?1?.
rev. 0.2 229 c8051f336/7/8/9 26. c2 interface c8051f336/7/8/9 devices in clude an on-chip silicon la bs 2-wire (c2) debug inte rface to allow flash pro - gramming and in-system debugging with the production pa rt installed in the end a pplication. the c2 inter - face uses a clock signal (c2ck) and a bi-directiona l c2 data signal (c2d) to transfer information between the device and a host system. see the c2 interfac e specification for details on the c2 protocol. 26.1. c2 interface registers the following describes the c2 registers necessary to perform flash programming through the c2 inter - face. all c2 registers are accessed through the c2 inte rface as described in the c2 interface specification. c2 register definition 26.1. c2add: c2 address bit 7 6 5 4 3 2 1 0 name c2add[7:0] type r/w reset 0 0 0 0 0 0 0 0 bit name function 7:0 c2add[7:0] c2 address. the c2add register is accessed via the c2 interface to select the target data register for c2 data read and data write commands. address description 0x00 selects the device id register for data read instructions 0x01 selects the revision id register for data read instructions 0x02 selects the c2 flash programming control register for data read/write instructions 0xb4 selects the c2 flash programm ing data register for data read/write instructions
c2 register definition 26.2. deviceid: c2 device id bit 7 6 5 4 3 2 1 0 name deviceid[7:0] type r/w reset 0 0 0 1 0 1 0 0 c8051f336/7/8/9 230 rev. 0.2 c2 address: 0x00 bit name function 7:0 deviceid[7:0] device id. this read-only register returns the 8-bit device id: 0x14 (c8051f336/7/8/9). c2 register definition 26.3. revid: c2 revision id bit 7 6 5 4 3 2 1 0 name revid[7:0] type r/w reset varies varies varies varies varies varies varies varies c2 address: 0x01 bit name function 7:0 revid[7:0] revision id. this read-only register returns the 8-bit revision id. for example: 0x00 = revision a.
c2 register definition 26.4. fpctl: c2 flash programming control bit 7 6 5 4 3 2 1 0 name fpctl[7:0] type r/w reset 0 0 0 0 0 0 0 0 rev. 0.2 231 c8051f336/7/8/9 c2 address: 0x02 bit name function 7:0 fpctl[7:0] flash programming control register. this register is used to enable flash programming via the c2 interface. to enable c2 flash programming, the following codes must be written in order: 0x02, 0x01. note that once c2 flash programming is ena bled, a system reset must be issued to resume normal operation. c2 register definition 26.5. fpdat: c2 flash programming data bit 7 6 5 4 3 2 1 0 name fpdat[7:0] type r/w reset 0 0 0 0 0 0 0 0 c2 address: 0xb4 bit name function 7:0 fpdat[7:0] c2 flash programming data register. this register is used to pass flash commands, addresses, and data during c2 flash accesses. valid commands are listed below. code command 0x06 flash block read 0x07 flash block write 0x08 flash page erase 0x03 device erase
c8051f336/7/8/9 232 rev. 0.2 26.2. c2 pin sharing the c2 protocol allows the c2 pins to be shared wi th user functions so that in-system debugging and flash programming may be performed. this is possible because c2 communication is typically performed when the device is in the halt state, where all on-chip peripherals and user software are stalled. in this halted state, the c2 interface c an safely ?borrow? the c2ck ( rst ) and c2d pins. in most applications, external resistors are required to isolate c2 interface traffic from the user application. a typical isolation configuration is shown in figure 26.1 . c2d c2ck /reset (a) input (b) output (c) c2 interface master c8051fxxx figure 26.1. typical c2 pin sharing the configuration in figure 26.1 assumes the following: 1. the user input (b) cannot change stat e while the target device is halted. 2. the rst pin on the target device is used as an input only. additional resistors may be necessary depending on the specific application.
rev. 0.2 233 c8051f336/7/8/9 n otes :
c8051f336/7/8/9 234 rev. 0.2 c ontact i nformation silicon laboratories inc. 400 west cesar chavez austin, tx 78701 tel: 1+(512) 416-8500 fax: 1+(512) 416-9669 toll free: 1+(877) 444-3032 email: mcuinfo@silabs.com internet: www.silabs.com the information in this document is believed to be accurate in al l respects at the time of publ ication but is subject to change without notice. silicon laboratories assumes no re sponsibility for errors and omissions, and disclaims responsibi lity for any consequen ces resulting from the use of information included herein. additi onally, silicon laboratories assume s no responsibility for the fun ction- ing of undescribed features or parameters. silicon laboratories reserves the right to make changes without further notice. sili con laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpos e, nor does silicon laboratories assume any liabi lity arising out of the application or use of any product or circuit, and specifi cally disclaims any and all liability, including without limitation consequential or incident al damages. silicon laboratories product s are not designed, intended, or authorized for use in applications in tended to support or sustain life, or for any other application in which the failure of the silicon laboratories product could create a si tuation where personal injury or death may occur. should buyer purchase or use silicon laboratories prod ucts for any such unintended or unauthorized application, buyer shall indemnify and hold silicon laboratories harmless against all claims and damages. silicon laboratories and silicon labs are trademarks of silicon laboratories inc. other products or brandnames mentioned herein are trademark s or registered trademarks of their respective holders

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